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Manufacturing method of coining template

A manufacturing method and a printing template technology, which are applied in the field of microelectronics, can solve problems such as difficult adjustment of sidewall inclination angles and top width of graphics, and inability to obtain photoresist graphics, etc., and achieve low process costs and good mechanical properties. Effect

Inactive Publication Date: 2016-06-08
BEIJING NAURA MICROELECTRONICS EQUIP CO LTD
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  • Claims
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Problems solved by technology

[0013] However, it can be seen from Figure A and Figure E that the pattern morphology of the photoresist obtained in the imprinting step is consistent with that of the photoresist sample obtained in the photolithography step, and as mentioned above, the photolithography process obtains The sidewall of the pattern is vertical, and it is difficult to adjust the inclination angle of the sidewall and the top width of the pattern. Therefore, the above-mentioned nanoimprinting method can only obtain the pattern with the vertical sidewall, but cannot obtain the "narrow top". bottom width" photoresist pattern morphology

Method used

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  • Manufacturing method of coining template

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Embodiment Construction

[0042] In order for those skilled in the art to better understand the technical solution of the present invention, the method for making the imprint template provided by the present invention will be described in detail below in conjunction with the accompanying drawings.

[0043] figure 2 It is a flow chart of the method for making the imprint template provided by the present invention. see figure 2 , the preparation method of imprint template provided by the present invention, it comprises the following steps:

[0044] In the mask photolithography step, a layer of photoresist mask is flattened on the master plate made of silicon material, and the required pattern is formed on the photoresist mask by photolithography process;

[0045] Graphic modification step, used to reduce the top width of graphics;

[0046] Master etching step, copying the graphics on the master;

[0047] The template making step is to make an imprint template by using the master plate with graphics...

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Abstract

The invention provides a manufacturing method of a coining template. The manufacturing method comprises following steps: a step of photo-mask lithography, wherein a mother set prepared from a silicon material is coated with a layer of photoresist mask film, and photoetching is adopted so as to form needed images on the photoresist mask film; a step of image modification, wherein image modification is used for reducing top width of the images; a step of mother set etching, wherein the images are copies onto the mother set; and a step of template preparation, wherein the mother set with the images is used for manufacturing the coining template. According to the manufacturing method, photoresist images with small top width and large bottom width are formed on the mother set, the coining template prepared using the mother set can be used for obtaining photoresist image morphologys with small top width and large bottom width on the photoresist mask film via nanoimprint lithography.

Description

technical field [0001] The invention relates to the technical field of microelectronics, in particular to a method for making an embossing template. Background technique [0002] PSS (Patterned Sapp Substrates, patterned sapphire substrate) technology is currently a commonly used method to improve the light extraction efficiency of GaN (gallium nitride)-based LED devices. During the PSS process, it usually grows a mask for dry etching on the substrate, and uses a photolithography process to carve the mask into a pattern; then uses ICP technology to etch the surface of the substrate to form the required pattern , and then remove the mask, and use the epitaxial process to grow a GaN film on the etched substrate surface. With the development of PSS technology, the requirements for the size of the pattern after etching are becoming increasingly stringent. For example, the etching depth of the pattern is required to be increased from the initial 1.5um to 1.8um, and the bottom wi...

Claims

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Application Information

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IPC IPC(8): G03F7/00
Inventor 谢秋实
Owner BEIJING NAURA MICROELECTRONICS EQUIP CO LTD
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