FPGA wiring method and device

Abstract

The invention discloses an FPGA wiring method and device. The method comprises the steps that a cost value between part of nodes in an FPGA is estimated, and a cost estimating model is generated; the cost estimating model is utilized for estimating the cost value between the nodes in the wiring process; wiring is carried out according to the estimation result. According to the technical scheme, the problem that an existing FPGA wiring scheme is not perfect enough is solved.

Description

technical field [0001] The invention relates to the technical field of field programmable gate array (FPGA), in particular to an FPGA wiring method and device. Background technique [0002] Since the advent of FPGA, its unique programmability has greatly simplified the process of traditional digital circuit design, and more and more electronic designers use FPGA chips to design electronic systems. As the scale of FGPA continues to expand, the performance requirements for software algorithms are also getting higher and higher. For example, a larger scale means a larger layout span and a more complex circuit netlist, which puts higher requirements on FPGA routing efficiency. Therefore, how to reduce the routing time to a minimum without affecting the performance becomes a factor that cannot be ignored in the routing algorithm. [0003] At present, the more common wiring algorithm is the A* algorithm, which uses the concept of cost function. Such as figure 1 In the node arr...

AI Technical Summary

Problems solved by technology

[0009] The present invention provides an FPGA wiring method and device, which solves the problem that the existing FPGA wiring scheme is not perfect enough

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