Formation method of semiconductor structure

Abstract

A method for forming a semiconductor structure, comprising: forming a gate stack structure on a semiconductor substrate; forming a stress layer on the semiconductor substrate to cover the gate stack structure; and performing ozone plasma treatment on the surface of the stress layer , to form a thin oxide layer on the surface of the stress layer; after the ozone plasma treatment, an interlayer dielectric layer is formed on the stress layer. The method can eliminate the problem of excessively high failure rate when the wafer is subjected to failure detection.

Description

technical field [0001] The invention relates to the field of semiconductor manufacturing, in particular to a method for forming a semiconductor structure. Background technique [0002] In the manufacture of semiconductor devices, the stress layer can be used to induce stress in the transistor channel, thereby adjusting the carrier mobility in the channel. Complementary Metal-Oxide-Semiconductor (CMOS) structures include NMOS structures and PMOS structures. For CMOS structures, it is necessary to deposit a stress layer with tensile stress on the NMOS structure, and deposit a stress layer on the PMOS structure. A stress layer with compressive stress, the stress layer is usually made of silicon nitride. [0003] With the reduction of the geometric size of semiconductor structures, high aspect ratio process (High AspectRatioProcess, HARP) is used to form interlayer dielectric layer to improve the gap-fill performance of interlayer dielectric layer (inter-layerdielectric, ILD) ...

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Problems solved by technology

[0004] However, after the high aspect ratio process is used to form the interlayer dielectric layer on the above-mentioned stress layer, no matter in the production line or offline, when the wafer is troubleshooted, the failure rate is too high. Especially serious when detecting particulate matter problems

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