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Formation method of semiconductor structure

A semiconductor and conductive layer technology, used in semiconductor/solid-state device manufacturing, electrical components, circuits, etc., can solve the problem that the electrical properties of semiconductor structures need to be improved, improve reliability and electrical properties, avoid etching damage, and improve hydrophobicity. sexual effect

Inactive Publication Date: 2016-06-22
SEMICON MFG INT (SHANGHAI) CORP
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  • Abstract
  • Description
  • Claims
  • Application Information

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Problems solved by technology

[0004] However, the electrical properties of semiconductor structures formed by existing technologies still need to be improved

Method used

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  • Formation method of semiconductor structure
  • Formation method of semiconductor structure

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Embodiment Construction

[0030] It can be seen from the background technology that the electrical performance of the semiconductor structure formed in the prior art needs to be improved. For example, the breakdown voltage (VBD: BreakdownVoltage) of the semiconductor structure is low, and there is a time-dependent dielectric breakdown (TDDB: TimeDependentDielectricBreakdown) problem.

[0031] It has been found through research that the dielectric layer is usually etched by a dry etching process to form an opening through the dielectric layer. During the dry etching process, impurities will be introduced into the opening, such as the reaction between the etching gas and the dielectric layer to generate reaction by-products. The product, the etching gas and the mask layer material (such as photoresist, organic distribution material, anti-reflection material) react to form reaction by-products, and part of the reaction by-products will fall on the bottom of the opening and the sidewall of the opening.

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Abstract

Provided is a formation method of a semiconductor structure. The method includes: a substrate and a dielectric layer positioned on the surface of the substrate are provided, and a bottom metal layer is arranged in the substrate; the dielectric layer is etched to form an opening penetrating through the dielectric layer, and the surface of the bottom metal layer is exposed at the bottom of the opening; pre-restoration irradiation processing of the dielectric layer at sidewalls of the opening is performed, and contact angles on the surface of the dielectric layer at the sidewalls of the opening are increased; after the pre-restoration irradiation processing, wet-process cleaning processing of the opening is performed; and a conductive layer filling the opening is formed. According to the method, the contact angles on the surface of the dielectric layer at the sidewalls of the opening are increased, the hydrophobicity capability of the surface of the dielectric layer at the sidewalls of the opening is improved, the corrosion of the dielectric layer at the sidewalls of the opening due to the wet-process cleaning processing is avoided, the breakdown voltage is increased, the problem of time dependent dielectric breakdown is suppressed, and the reliability and the electrical performance of the semiconductor structure are enhanced.

Description

technical field [0001] The invention relates to the technology in the field of semiconductor manufacturing, in particular to a method for forming a semiconductor structure. Background technique [0002] With the continuous advancement of VLSI process technology, the feature size of semiconductor devices has been continuously reduced, and the chip area has continued to increase. The delay time of the interconnect structure can be compared with the device gate delay time. People are faced with the problem of how to overcome the significant increase in RC (R refers to resistance, C refers to capacitance) delay due to the rapid increase in connection length. In particular, due to the increasing influence of the capacitance between metal wirings, the performance of the device is greatly reduced, which has become a key restrictive factor for the further development of the semiconductor industry. In order to reduce the RC delay caused by interconnection, various measures have been...

Claims

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Application Information

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IPC IPC(8): H01L21/768
Inventor 张海洋胡敏达
Owner SEMICON MFG INT (SHANGHAI) CORP
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