Semiconductor structure and forming method therefor

Abstract

The invention discloses a semiconductor structure and a forming method therefor. The method comprises the steps: providing a substrate; forming an isolation structure on the substrate, wherein the isolation structure is used for dividing the substrate into a first region and a second region; forming a first well region in the first region of the substrate; forming a second well region in the second region of the substrate, wherein the doping type of the second well region is different from the doping type of the first well region; forming a pseudo grid structure located on the isolation structure; taking the pseudo grid structure as a mask, and forming a second heavily-doped region in the second well region, wherein the doping type of the second heavily-doped region is the same as the doping type of the second well region; taking the pseudo grid structure as the mask, and forming a first heavily-doped region in the first well region, wherein the doping type of the first heavily-doped region is the same as the doping type of the first well region. The method forms the pseudo grid structure on the isolation structure at the junction of the first and second regions, and the pseudo grid structure can serve as an ion injection mask during the forming of the doped regions, thereby preventing doping ions in the heavily-doped regions from entering the adjacent well region or heavily-doped region, and improving the breakdown voltage of an adjacent device.

Description

technical field [0001] The invention relates to the field of semiconductors, in particular to a semiconductor structure and a forming method thereof. Background technique [0002] In the manufacturing process of semiconductor devices, Shallow Trench Isolation (STI) or Local Oxidation of Silicon (LOCOS) is often used as the well isolation structure between the P well (Pwell) and the N well (Nwell). to achieve device isolation. Two adjacent well regions are formed in the substrate, a heavily doped region is also formed in the corresponding well regions, an isolation structure is formed between the adjacent well regions, and the depth of the adjacent well regions is greater than the isolation structure depth. Through the well isolation structure, the punch-through of adjacent devices can be suppressed, and the leakage of devices can be reduced. [0003] However, the well isolation structure in the prior art tends to cause the degradation of electrical performance of the semi...

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Problems solved by technology

[0003] However, the well isolation structure in the prior art is likely to ca

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