Shifting register and light-emitting control circuit
A shift register, capacitor technology, applied in static memory, digital memory information, instruments, etc., can solve the problems of signal line crosstalk, adverse effects on stability and reliability, clock signal multiplication, etc.
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[0043] Example 1
[0044] Please refer to figure 1 In a preferred embodiment of the present invention, the shift register unit circuit includes two input clock ports (including a first clock signal CK, a second clock signal CKB), a signal input terminal IN, an output port OUT and a constant voltage Signals VGH (high level), VGL (low level). The schematic diagram of the shift register circuit is as follows figure 1 Shown.
[0045] This schematic diagram consists of 8 P-channel thin film transistors (M1~M8) and 3 capacitors (C1~C3). For the sake of brevity of the schematic diagram, even if there is no direct connection, all nodes with the same name in the diagram are connected together. The schematic structure is described as follows:
[0046] The gate of the first thin film transistor is connected to the signal input terminal IN, the first source / drain is connected to VGH, and the second source / drain is connected to the NET1 node;
[0047] The gate of the second thin film transisto...
Example Embodiment
[0067] Example 2
[0068] Please refer to image 3 A light-emitting control circuit includes a plurality of shift registers connected in cascade. The circuit after cascading is like image 3 As shown, the shift register units at all levels are consistent. Specifically, the output port of the previous stage is connected to the input port of the next stage. EM(N) is the output signal of the Nth stage, and is also used as the input signal of the N+1th stage. The input clock port connection of each stage is different. The connection of the three input clock ports of each level is described as follows: the first clock signal of the first level is connected to CK, the second clock signal is connected to CKB; the first clock signal of the second level is connected to CKB, the second clock signal is connected to CK, and the third The connection method of the stage is the same as that of the first stage, and the connection method of the fourth stage is the same as that of the second s...
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