Epitaxial wafer manufacturing method and epitaxial wafer

A technology of epitaxial wafers and manufacturing methods, applied in semiconductor/solid-state device manufacturing, electrical components, circuits, etc., can solve problems such as poor crystallinity of the wafer surface, uncaptured gettering regions, and epitaxial layer defects, etc., to achieve the suppression of epitaxial Effect of defect formation, excellent gettering ability

Active Publication Date: 2019-06-18
SUMCO CORP
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  • Abstract
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Problems solved by technology

[0008] However, when an epitaxial layer is formed on a silicon wafer or when a device element is formed on a device formation region, if contaminating metals adhere to the wafer surface, the contaminating metals cannot be detached from the device formation region due to the lowering of the temperature of the device formation process described above. May not be trapped into gettering regions that exist deep from the wafer surface
[0009] In addition, in order to form a gettering layer by implanting carbon ions at a high concentration at a position deep from the wafer surface, the accelerating voltage of the carbon ions must be increased. defect problem

Method used

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  • Epitaxial wafer manufacturing method and epitaxial wafer
  • Epitaxial wafer manufacturing method and epitaxial wafer
  • Epitaxial wafer manufacturing method and epitaxial wafer

Examples

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Embodiment

[0069] (Invention Example 1-Invention Example 3)

[0070] Examples of the present invention will be described below.

[0071] First, as a substrate of an epitaxial wafer, a silicon wafer having a diameter of 300 mm, a thickness of 775 μm, and a resistivity of about 0.003 Ω·cm was prepared. Next, using a cluster ion generator (manufactured by Nisshin Ion Machinery Co., Ltd., model: CLARIS), generate C 3 h 5 The clusters were irradiated on the surface of the silicon wafer as cluster ions under the condition that the acceleration voltage per carbon atom was 23.4 keV / atom. Here, the dose of cluster ions is 1.0×10 15 atom / cm 2 (Invention Example 1), 5×10 15 atom / cm 2 (Invention Example 2), 2×10 14 atom / cm 2 (invention example 3) these three levels. Next, the silicon wafer was transported to a monolithic epitaxial growth apparatus (manufactured by Applied Materials, Inc.), and hydrogen baking was performed at a temperature of 1120° C. for 30 seconds in the apparatus. The...

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Abstract

Provided is a method for manufacturing an epitaxial wafer having excellent gettering capability while suppressing the formation of epitaxial defects. It is characterized in that it has the following process: cluster ion irradiation process, with 2.0×10 14 / cm 2 Above 1.0×10 16 / cm 2 The following dose irradiates cluster ions 16 containing at least carbon to the surface of silicon wafer 10 having a resistivity of 0.001 Ω·cm or more and 0.1 Ω·cm or less, and the constituent elements forming cluster ions 16 form a solid solution on the surface of silicon wafer 10 to form a solid solution. and an epitaxial layer forming step of forming an epitaxial layer 20 having a resistivity higher than that of the silicon wafer 10 on the modified layer 18 of the silicon wafer 10 .

Description

technical field [0001] The present invention relates to a manufacturing method of an epitaxial wafer and an epitaxial wafer, in particular to a manufacturing method of an epitaxial wafer that suppresses the formation of epitaxial defects and has excellent gettering capability. Background technique [0002] In recent years, the miniaturization of silicon devices has been progressing, and it is required that there be no crystal defects in the device formation region that increase the leakage current and shorten the lifetime of the carrier. In order to meet this requirement, an epitaxial wafer is manufactured in which an epitaxial layer is grown on a silicon wafer, and the epitaxial layer on the surface is used as a device formation region. [0003] One of the problems in the silicon device manufacturing process is the contamination of heavy metals into the wafer. For example, when heavy metals such as cobalt, copper, or nickel are mixed into the wafer, it will cause poor dwel...

Claims

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Application Information

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Patent Type & Authority Patents(China)
IPC IPC(8): H01L21/322H01L21/20H01L21/265
CPCH01L21/26506H01L21/26566H01L21/3221H01L21/02381H01L21/02447H01L21/02532H01L21/0262H01L21/02658H01L21/02694H01L29/36
Inventor 岩永卓朗栗田一成门野武
Owner SUMCO CORP
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