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MOSFET device manufacturing method

A manufacturing method and device technology, applied in semiconductor/solid-state device manufacturing, semiconductor devices, electrical components, etc., can solve the problems of large size of MOSFET devices, and achieve the effects of low cost, reduced production cost, and reduced volume

Inactive Publication Date: 2016-11-23
PEKING UNIV FOUNDER GRP CO LTD +1
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  • Summary
  • Abstract
  • Description
  • Claims
  • Application Information

AI Technical Summary

Problems solved by technology

[0005] The present invention provides a method for manufacturing a MOSFET device to try to solve the problem of large MOSFET devices in the prior art

Method used

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  • MOSFET device manufacturing method

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Embodiment 1

[0032] This embodiment provides a method for manufacturing a MOSFET device, such as figure 1 Shown is a schematic flow chart of the fabrication method of the MOSFET device according to this embodiment. The fabrication method of the MOSFET device of the present embodiment comprises:

[0033] Step 101 , forming a deep groove in a substrate, the substrate includes a substrate of a first conductivity type, a first structure layer of the first conductivity type, and a second structure layer of a second conductivity type sequentially formed from bottom to top.

[0034] In this embodiment, the way to form the deep trench may be ion etching. For example, a mask layer is first formed on the substrate, and the substrate is etched until the substrate is exposed by using the mask layer as a mask to form deep grooves. When forming the mask layer, deposition and photolithography processes can be used. The mask layer can be removed later.

[0035] It should be pointed out that the deep g...

Embodiment 2

[0049] This embodiment provides a further supplementary description of the fabrication method of the MOSFET device in the above embodiments. like Figures 2A-2J Shown is a structural schematic diagram of each step of the method for fabricating a MOSFET device according to this embodiment.

[0050] like Figure 2A As shown, a first oxide layer 202 is formed on a substrate 201 .

[0051] The base 201 of this embodiment includes an N-type substrate 2011 , an N-type epitaxial layer 2012 and a P-type epitaxial layer 2013 which are sequentially formed from bottom to top. It should be noted that the present embodiment only shows the base 201 in an exemplary manner, and the contents shown in the base 201 can be replaced by corresponding P-type dopants and materials by replacing N-type dopants and materials, and vice versa .

[0052] The base 201 can be formed by first forming an N-type substrate 2011, then forming an N-type epitaxial layer 2012 on the N-type substrate 2011 through...

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Abstract

The invention provides an MOSFET device manufacturing method. The method includes forming a deep groove in a base, wherein the base includes a substrate of a first conducting type, a first structural layer of the first conducting type and a second structural layer of a second conducting type successively from bottom up; forming an oxidation layer on the side wall of the deep groove; forming a third structural layer of the second conducting type in the deep groove, wherein the top part of the third structural layer is lower than that of the base; and forming a deep groove grid electrode on the third structural layer and in the deep groove. According to the manufacturing method provided by the invention, the size of an MOSFET device can be reduced and the production cost of the MOSFET device can also be reduced.

Description

technical field [0001] The invention relates to semiconductor technology, in particular to a method for manufacturing a MOSFET device. Background technique [0002] In a MOSFET (Metal Oxide Semiconductor Field Effect Transistor, MOSFET) device, the power loss is generally reduced by reducing the on-resistance of the device. [0003] Since the breakdown voltage is inversely proportional to the on-resistance, when the on-resistance decreases, it will have an adverse effect on the breakdown voltage. In order to solve this problem, a super junction power MOSFET is introduced in the prior art, which includes alternately formed P-type regions and N-type regions located below the active region of the super junction power MOSFET. Under ideal conditions, the alternating P-type regions and N-type regions in super junction power MOSFETs should be in a state of charge balance, so that the P-type regions and N-type regions are mutually depleted under reverse voltage conditions, and the ...

Claims

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Application Information

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Patent Type & Authority Applications(China)
IPC IPC(8): H01L21/336H01L21/28
CPCH01L29/66477H01L21/28017H01L29/66484
Inventor 赵圣哲
Owner PEKING UNIV FOUNDER GRP CO LTD