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Edge-trimmed composite back sealing layer structure used for silicon wafer, and manufacturing method thereof

A manufacturing method and layer structure technology, applied in semiconductor/solid-state device manufacturing, semiconductor/solid-state device components, semiconductor devices, etc., can solve problems such as pyramids, edge stacking faults, and particle pollution

Inactive Publication Date: 2016-11-23
SHANGHAI SHENHE THERMO MAGNETICS ELECTRONICS CO LTD
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  • Summary
  • Abstract
  • Description
  • Claims
  • Application Information

AI Technical Summary

Problems solved by technology

[0004] The object of the present invention is to provide a composite back-sealing layer structure with edge removal for silicon wafers and its manufacturing method that solves the problems of particle contamination, edge stacking faults, and pyramids caused by delamination.

Method used

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  • Edge-trimmed composite back sealing layer structure used for silicon wafer, and manufacturing method thereof
  • Edge-trimmed composite back sealing layer structure used for silicon wafer, and manufacturing method thereof
  • Edge-trimmed composite back sealing layer structure used for silicon wafer, and manufacturing method thereof

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Embodiment Construction

[0017] The composite back-sealing layer structure with edge removal and its manufacturing method for silicon wafers according to the present invention will be further described in detail in conjunction with the accompanying drawings.

[0018] Such as image 3 , Figure 4 As shown, the compound back-sealing layer structure with edge removal used in the present invention for silicon wafers completely covers the polysilicon back-sealing layer 7 on the back side 1, back bevel region 2, and edge region 3 of the silicon wafer. The outer side of the polysilicon back-sealing layer 7 on the back side 1 of the silicon wafer is covered with a silicon dioxide back-sealing layer 6 . The front side 5 of the silicon wafer is the polishing surface. The bevel region 4 on the front side of the silicon wafer is a smooth monocrystalline silicon surface without polycrystalline silicon film coverage. The polysilicon back-sealing layer 7 covers the back side 1, the back bevel area 2 and the edge ...

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Abstract

The invention discloses an edge-trimmed composite back sealing layer structure used for a silicon wafer. The edge-trimmed composite back sealing layer structure comprises a polysilicon back sealing layer and a silicon dioxide back sealing layer, wherein the polysilicon back sealing layer covers the back surface, back surface bevel edge regions and fringe regions of the silicon wafer; the silicon dioxide back sealing layer covers the polysilicon back sealing layer and is positioned on the back surface of the silicon wafer. According to the edge-trimmed composite back sealing layer structure used for the silicon wafer, only monocrystal silicon serving as a body material is left on the front surface bevel edge of the silicon wafer, and the front surface bevel edge has a smooth surface with high quality, which makes almost no difference from a polished surface. Only the monocrystal silicon layers are grown on the front surface bevel edge of the silicon wafer and the polished surface in epitaxial processing, seamless connection can be achieved, the layered phenomenon cannot occur, and the problems of particle contaminant, edge stacking fault and pyramid in epitaxial processing can be solved, thereby increasing the yield in manufacturing process.

Description

technical field [0001] The invention relates to the fields of semiconductor and material production and application, in particular to a compound back-sealing layer structure with edge removal for silicon wafers and a manufacturing method thereof. Background technique [0002] The back seal design of the silicon wafer has an important impact on the subsequent epitaxial process. Improper back seal design will cause problems such as self-doping and abnormal growth of silicon slag on the back, resulting in the loss of the yield of the epitaxial process. figure 1 and figure 2 Shown is a common back-sealing design for silicon wafers with edge removal treatment, which adopts the composite back-sealing layer design of inner polysilicon back-sealing + outer silicon dioxide back-sealing. Among them, the polysilicon back-sealing layer plays the role of external gettering, and the silicon dioxide back-sealing layer plays the role of back-sealing. [0003] However, since the silicon w...

Claims

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Application Information

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Patent Type & Authority Applications(China)
IPC IPC(8): H01L23/29H01L23/31H01L21/56
Inventor 千津井勝己贺贤汉洪漪
Owner SHANGHAI SHENHE THERMO MAGNETICS ELECTRONICS CO LTD
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