Low-power-consumption scanning testing method and device based on parallel applying of test excitation

Abstract

The invention discloses a low-power-consumption scanning testing method and device based on the parallel applying of test excitation, and the method comprises the steps: S1, enabling a scanning unit in a tested circuit to be divided and built into a plurality of scanning links with equal lengths; S2, sequentially applying a testing enabling signal and testing clock pulse to each scanning link till the traversal of all scanning links is completed; S3, applying a capturing clock to all links at the same time, capturing the response output of the scanning units in all scanning links at the same time, and sequentially outputting the captured response output. The low-power-consumption scanning testing implements the method. The device comprises a scanning link building module, a scanning excitation module and a scanning capturing module. The method is simple in implementation, is high in flexibility, is low in power consumption, is short in testing time, and can be suitable for the scanning testing of a plurality of scanning links.

Description

technical field [0001] The invention relates to the technical field of scan test of integrated circuits, in particular to a low power consumption scan test method and device. Background technique [0002] With the further reduction of the size of the integrated circuit process, the manufacturing yield is becoming more and more difficult to guarantee, and the design for test has become an increasingly indispensable technology for the development and manufacture of today's chips. However, because the fault test emphasizes high fault coverage and short test time, the flip probability of the internal logic of the chip caused by the stimulus of the fault test is much greater than that of the internal logic of the chip in the normal function mode, resulting in several times the power consumption of the test power consumption in normal functional mode. If the chip is in a state of high power consumption for a long time during the test process, or if the peak power consumption exce...

AI Technical Summary

Problems solved by technology

[0009] 1. The huge shift power consumption of the scan unit in the serial shift mode: due to the above-mentioned testability design of the traditional multi-scan chain structure, a large number of serial shift operations will be performed in the scan test mode, but any test stimulus (or Test response) in 0 → 1 or 1 → 0 jump, will be passed along each scan unit on the scan chain until the group of test stimuli is applied (or the capture response of the previous group of stimuli is completely removed);

[0010] 2. Huge dynamic power consumption of combinatorial logic in serial shift mode: due to the frequent flipping of the value of the scan unit (take the scan flip-flop as an example) in the testability design of the above-mentioned traditional multi-scan chain structure, the scan flip-flop The combinational logic driven by the Q terminal will also jump due to the jump of the Q terminal value, thereby generating unnecessary combinational logic flipping power consumption

[0011] 3. The huge power consumption of the clock tree during the test: by figure 2 It can be seen that during the entire test process, the test clock of each scan chain is active. For large-scale chip design, the power consumption of the clock tree will account for a large part

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