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Selection Method of Polysilicon Dry Etching Process for Embedded Flash Memory

A polysilicon, embedded technology, applied in the direction of semiconductor devices, electrical components, circuits, etc., can solve the problems that the thickness of the oxide layer does not meet expectations, and the control of the tip of the floating gate is not accurate enough, so as to achieve the effect of precise control of the shape

Active Publication Date: 2019-07-02
SHANGHAI HUAHONG GRACE SEMICON MFG CORP
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Problems solved by technology

[0006] However, for new products, it is difficult to select the correct dry etching process through pre-judgment only through the layout of the active area, or only through the layout of the floating gate area, resulting in the thickness of the obtained oxide layer not meeting expectations. Control is not precise enough

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  • Selection Method of Polysilicon Dry Etching Process for Embedded Flash Memory
  • Selection Method of Polysilicon Dry Etching Process for Embedded Flash Memory
  • Selection Method of Polysilicon Dry Etching Process for Embedded Flash Memory

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Embodiment Construction

[0023] As mentioned above, in embedded flash memory, the height and sharpness of the tip of the floating gate will affect the coupling voltage of the floating gate during programming and erasing, thereby affecting the performance of the flash memory during programming and erasing. Specifically, the tip of the floating gate that is too low and blunt will lead to too small tunneling current, and then the programming and erasing time will be too long because the electric field strength is too low and the programming and erasing current is too small.

[0024] In a specific process implementation, the accuracy of the tip of the floating gate can be known from the accuracy of the thickness of the oxide layer remaining on the active region after the polysilicon dry etching process. Specifically, the thinner the residual oxide layer is, the more severe the polysilicon dry etching is on the tip of the floating gate, which is more likely to cause the tip of the floating gate to be too lo...

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Abstract

A method for selecting a polysilicon dry etching process of an embedded flash memory, the method comprising the following steps: providing the layout of the active region and the layout of the floating gate region of the embedded flash memory; The layout of the gate region determines the layout density of the actual etching area of ​​the active area and the floating gate area, and the actual etching area is the area where polysilicon is etched by a dry etching process; according to the layout density of the actual etching plate area and the preset thickness of the oxide layer under the polysilicon after etching, and select a corresponding dry etching process. According to the layout density of the actual etching area of ​​the polysilicon, the solution of the present invention can select a suitable polysilicon dry etching process, so as to precisely control the tip of the floating gate, so as to improve the performance of the flash memory.

Description

technical field [0001] The invention relates to the field of semiconductor manufacturing technology, in particular to a method for selecting a polysilicon dry etching process for an embedded flash memory. Background technique [0002] In embedded flash memory, the height and sharpness of the tip of the floating gate will affect the coupling voltage of the floating gate during programming and erasing, thereby affecting the performance of the flash memory during programming and erasing. Therefore, precise control of the tip of the floating gate is of great significance for controlling the performance of flash memory. In the implementation of the specific process, the tip of the floating gate can be known through the accuracy of the thickness of the oxide layer (such as silicon dioxide, silicon nitride, etc.) remaining on the active region after the polysilicon dry etching process (Poly Dry-Etch). Is it accurate. [0003] In the prior art, for a certain product, a polysilicon...

Claims

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Application Information

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Patent Type & Authority Patents(China)
IPC IPC(8): H01L27/11517H01L21/3065H01L21/28H10B41/00
CPCH01L21/28H01L21/3065H10B41/00
Inventor 孙访策李志国杨勇黄冲邬镝
Owner SHANGHAI HUAHONG GRACE SEMICON MFG CORP
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