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Manufacturing method of passivation layer of high-voltage chip

A technology of high-voltage chips and manufacturing methods, which is applied in semiconductor/solid-state device manufacturing, electrical components, and electrical solid-state devices, etc. performance and reliability issues, to achieve the effect of process optimization, stress reduction, and easy realization

Inactive Publication Date: 2017-01-04
GLOBAL ENERGY INTERCONNECTION RES INST CO LTD +2
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  • Abstract
  • Description
  • Claims
  • Application Information

AI Technical Summary

Problems solved by technology

Thinning of the back side can easily cause warpage of the high-voltage chip to increase, and the stress of the chip changes greatly before and after thinning, resulting in poor adhesion of the passivation layer material, which can easily affect the performance and reliability of the high-voltage chip

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  • Manufacturing method of passivation layer of high-voltage chip
  • Manufacturing method of passivation layer of high-voltage chip
  • Manufacturing method of passivation layer of high-voltage chip

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Embodiment Construction

[0041] The passivation layer manufacturing technique includes the steps of passivation layer deposition, passivation layer photolithography, passivation layer etching and passivation layer annealing / curing. Passivation layer manufacturing technology is generally after the front side of the wafer is processed, and the passivation layer is generally deposited on the metal layer. Passivation layer photolithography and passivation layer corrosion complete the formation of passivation layer, the exposed area of ​​passivation layer is the subsequent packaging wiring area, and the exposed area should be as small as possible under the condition of ensuring wiring (taking 1200V / 75A chip as an example, the area of ​​wiring The line shall be at least four 3.5×3.0mm2 rectangular areas). The annealing / curing of the passivation layer is generally a low-temperature process (taking polyimide passivation as an example, the curing temperature of the passivation layer is less than 500°C to provi...

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Abstract

The present invention relates to a manufacturing method of the passivation layer of a high-voltage chip. The method includes the following steps that: the front surface of the high-voltage chip is manufactured; back surface thinning processing is carried out; the passivation layer of the high-voltage chip is manufactured; and the back surface of the high-voltage chip, which is thinned, is manufactured. According to the manufacturing method provided by the technical schemes of the invention, the processing of the passivation layer is optimized in the manufacturing process of the high-voltage chip, and therefore, the stress of the chip can be decreased, the adhesion of the passivation layer and the chip can be strengthened, and the reliability of the passivation layer in subsequent processing and application can be improved, and the reliability of the high-voltage chip can be improved.

Description

technical field [0001] The invention relates to a manufacturing method of a semiconductor device, in particular to a manufacturing method of a high-voltage chip passivation layer. Background technique [0002] The exposed chip is susceptible to the influence of the external environment, resulting in the drift of the chip's electrical performance, failure or reduced reliability. In order to isolate the influence of the external environment, a passivation layer is usually formed on the surface of the chip during chip processing or subsequent packaging process to protect the chip and improve the reliability of the chip. The present invention mainly discusses the passivation layer formed on the chip surface during chip processing. Passivation layer materials include silicon dioxide, semi-insulating polysilicon, silicon nitride, polyimide, photoimide, aluminum oxide, etc. [0003] High-voltage chips (≥600V) work at high temperature and high voltage, and are more sensitive to th...

Claims

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Application Information

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IPC IPC(8): H01L23/31H01L21/56
CPCH01L23/3171H01L21/56
Inventor 刘江赵哿高明超王耀华乔庆楠吴迪何延强刘钺杨曹功勋李晓平董少华李立金锐温家良
Owner GLOBAL ENERGY INTERCONNECTION RES INST CO LTD
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