A system and method for realizing message processing based on fpga

Abstract

The present invention provides a message processing system based on FPGA, including a message aggregation module and a message forwarding module, a line side port and a plurality of system side ports, the input terminals of the message aggregation module are respectively connected to the plurality of system The output end of the message aggregation module is connected to the line side port; the input end of the message forwarding module is connected to the line side port, and the output end of the message forwarding module is connected to the line side port respectively. The multiple system side ports are connected, the message aggregation module and the message forwarding module both include a multi-level cache unit, and the message aggregation module and the message forwarding module divide the cache into multi-level caches and according to the message Flow selection data processing width. The invention also provides a message processing method based on FPGA. The system structure provided by the present invention is simpler, and the modular design effectively solves the problem of data bandwidth and cache modules being numerous and internal resources evenly distributed.

Description

technical field [0001] The invention belongs to the field of network communication, in particular to a message processing system and method based on FPGA. Background technique [0002] With the development of network technology, the wide application of 100G high-speed interface technology brings great opportunities for network equipment upgrades. Future 400G interface applications, chip and equipment manufacturers' interface upgrades will also lead to some interface problems. When the 100G interface is used, some application scenarios forward the port data to the internal 10G port. Data needs to be forwarded to 12 10G ports on the system side. FPGA realizes the high-speed interface and can realize the application of the high-speed interface in a low-cost way. However, in this packet switching structure that does not match the port rate, FPGA is faced with internal complex wiring restrictions, and it is often difficult to obtain normal timing results. When FPGA internal d...

AI Technical Summary

Problems solved by technology

However, in this packet-switching structure that does not match the port rate, the FPGA is faced with internal complex wiring constraints, and it is often difficult to obtain normal timing results.

When FPGA internal data cache uses block ram to realize large data flow, many block rams need to be used together. At the same time, data forwarding from 100G line speed to 12 ports requires data exchange of all data caches, which makes a large number of wiring resources complicated to use internally.

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