FPGA (Field-Programmable Gate Array) chip for realizing V-BY-ONE and corresponding V-BY-ONE (Video By ONE) processing method

Abstract

The embodiment of the invention discloses an FPGA (Field-Programmable Gate Array) chip for realizing V-BY-ONE and a corresponding V-BY-ONE (Video By ONE) processing method. The FPGA chip only contains a crystal oscillator. Same single-end clock information is transmitted to all of a plurality of high-speed transceiving units through the crystal oscillator. The single-end clock information is converted into uniform clock information through PLL units. The uniform clock information is sent to a V-BY-ONE mapping unit and V-BY-ONE transmission groups of various channels. Clock unification is carried out on different channels in a multi-channel FPGA chip with the plurality of high-speed transceiving units, processing processes of various channels are carried out synchronously, and the influence of multi-channel clock skews on the V-BY-ONE processing effect is avoided.

Description

technical field [0001] This application relates to the field of touch control, in particular to an FPGA chip for implementing V-BY-ONE and a corresponding V-BY-ONE processing method. Background technique [0002] V-By-ONE (Video By ONE) is a digital interface standard specially developed for image transmission. Compared with the traditional LVDS (Low-Voltage Differential Signaling, low-voltage differential signal) interface, the use of V-By-ONE to transmit video signals can help reduce PCB (Printed Circuit Board, printed circuit board) wiring and reduce EMI (Electro Magnetic Interference, electromagnetic interference) / EMC (Electromagnetic Compatibility, electromagnetic compatibility) interference, especially when transmitting ultra-high-definition images, the effect is more obvious. V-By-ONE is a transmission interface widely used in ultra-high-definition solutions. [0003] Since the SOC (System on Chip, system on chip) chip is a customized integrated circuit, the analog ...

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Problems solved by technology

[0007] In the scenario where FPGA is used to implement V-By-ONE, due to the change of high-speed transceiver unit specifications and cost considerations, the existing technology has changed the original design of V-By-ONE, through two or more V-By- The ONE controller is used to output to different high-speed transceiver units. Such a solution can no longer meet the stability requirements of the system due to the independent operation of each group of V-By-ONE controllers and high-speed transceiver units, resulting in abnormal decoding at the receiving end. Seriously affected the transmission quality and user experience of high-definition data

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