Method of manufacturing air gap/copper interconnection structure

Abstract

A method of manufacturing an air gap / copper interconnection structure comprises the following steps: providing a semiconductor substrate, completing a CMOS device front-end process on the semiconductor substrate, and forming a conventional first medium / copper interconnection structure on the semiconductor substrate; carrying out surface treatment on the conventional first medium / copper interconnection structure in a nitrogen atmosphere, and forming a layer of nitrogen-containing compound of copper on the surface of a copper interconnection line; using an etching device to etch a first medium in the middle of the copper interconnection line, wherein the first medium is etched with a fluorine-based gas and an oxygen-based gas, and the layer of nitrogen-containing compound of copper protects the copper interconnection line from exposure in the etching gas atmosphere; using wet solution to remove residual photoresist, and carrying out cleaning; and depositing a second medium to form an air gap / copper interconnection structure.

Description

technical field [0001] The invention relates to the field of semiconductor processing and manufacturing, in particular to a manufacturing method of an air gap / copper interconnection structure. Background technique [0002] With the continuous development of Moore's Law, the characteristic line width of transistors is getting smaller and smaller, the integration density is getting higher and higher, and the performance is getting stronger and stronger. For a complementary metal oxide semiconductor (Complementary Metal Oxide Semiconductor, CMOS for short) transistor, speed is an important index to characterize its performance. [0003] It is clear to those skilled in the art that the speed of CMOS is related to the delay of CMOS, and the delay of CMOS can be subdivided into the delay of the front-end device and the delay of the back-end interconnection line; and, as the semiconductor process size decreases, the back-end interconnection line The influence of the CMOS delay is ...

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Problems solved by technology

[0018] In view of the deficiencies in the prior art, the purpose of the present invention is to provide a manufacturing method of an air gap / copper interconnection structure to solve the problem of transistor performance deterioration caused by the existence of barrier layer "ears" in the prior art, which avoids The production of the barrier layer "ear" is not only beneficial to the chemical vapor deposition process to deposit the medium and form an air gap, but also improves the performance of the transistor

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