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Semiconductor device and forming method thereof

A semiconductor and device technology, applied in the field of semiconductor devices and their formation, to achieve the effect of improving ability, improving position accuracy and shape accuracy, and avoiding holes

Inactive Publication Date: 2017-05-10
SEMICON MFG INT (SHANGHAI) CORP +1
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  • Summary
  • Abstract
  • Description
  • Claims
  • Application Information

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Problems solved by technology

[0004] However, the performance of semiconductor devices formed in the prior art needs to be further improved

Method used

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  • Semiconductor device and forming method thereof
  • Semiconductor device and forming method thereof
  • Semiconductor device and forming method thereof

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Experimental program
Comparison scheme
Effect test

Embodiment Construction

[0033] It can be seen from the background art that the performance of semiconductor devices formed in the prior art needs to be further improved.

[0034] research findings, reference figure 1 and figure 2 , figure 1 It is a top view of a semiconductor device in the prior art, figure 2 for figure 1 A cross-sectional view along the XX1 direction, the process steps of forming the semiconductor device include: providing a substrate 101, a fin 102 located on the surface of the substrate 101, an isolation layer 103 located on the surface of the substrate 101 and the sidewall surface of the fin 102, and The top of the isolation layer 103 is lower than the top of the fin 102, across the gate structure 113 of the fin 102, and the gate structure 113 covers part of the top surface and the sidewall surface of the fin 102, wherein the gate structure There is an interconnection region on both sides, respectively located in the source region or drain region in the fins 102 on both ...

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Abstract

The invention provides a semiconductor device and a forming method thereof. The forming method of the semiconductor device includes providing a substrate, a gate structure being formed on the surface of the substrate, both sides of the gate structure each having an interconnection region, source regions and drain regions located at both sides of the gate structure being formed in the substrate of the interconnection region, and each interconnection region stretching across a plurality of source regions or a plurality of drain regions; forming first medium layers on the surface of the substrate and the surface of the gate structure; etching the first medium layers located on the interconnection regions till the source region surfaces or drain region surfaces are exposed, forming through holes being formed in the intersection regions, and each through hole stretching across all the source regions or all the drain regions in an interconnection region; forming interconnection layers filling the through holes; and forming zeroth conducting layers on top surfaces of the interconnection layers, each zeroth conducting layer being electrically connected with all the source regions or all the drain regions in an interconnection region. The forming method of the semiconductor device increases process flexibility, and improves electrical properties of the semiconductor device that is formed.

Description

technical field [0001] The invention relates to the technical field of semiconductor manufacturing, in particular to a semiconductor device and a forming method thereof. Background technique [0002] The metal interconnection structure is an indispensable structure in semiconductor devices, which is used to realize the interconnection between active regions, the interconnection between transistors, or the interconnection between different layers of metal lines, Complete signal transmission and control. Therefore, in the semiconductor manufacturing process, the formation of the metal interconnection structure has a great influence on the performance of the semiconductor device and the semiconductor manufacturing cost. In order to increase the density of devices, the size of semiconductor devices in integrated circuits has been continuously reduced. In order to realize the electrical connection of various semiconductor devices, a multi-layer interconnection structure is usual...

Claims

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Application Information

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Patent Type & Authority Applications(China)
IPC IPC(8): H01L21/768
CPCH01L21/768H01L21/76805H01L21/76838
Inventor 沈忆华余云初傅丰华潘见
Owner SEMICON MFG INT (SHANGHAI) CORP