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Data packet verification method and data packet verification system

A verification method and verification system technology, applied in transmission systems, user identity/authority verification, electrical components, etc., can solve problems such as difficulty in further improving detection speed and difficulty in checking massive network data packets

Inactive Publication Date: 2017-05-10
SHENZHEN PANGO MICROSYST CO LTD
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  • Summary
  • Abstract
  • Description
  • Claims
  • Application Information

AI Technical Summary

Problems solved by technology

[0003] On the server, the software-based regular expression executes commands in serial order. Today, with the development and popularization of the Internet, it becomes more and more difficult for the server to check massive network data packets, and it is difficult to further improve the detection speed.

Method used

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  • Data packet verification method and data packet verification system
  • Data packet verification method and data packet verification system

Examples

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no. 1 example

[0042] figure 1 It is a schematic structural diagram of the data packet verification system provided by the first embodiment of the present invention, consisting of figure 1 It can be seen that, in the present embodiment, the data packet verification system provided by the present invention includes: server 1 and FPGA2, and FPGA2 includes network data packet distribution matrix module 21, a plurality of data packet micro-nucleus judgment modules 22, control module 23, regular expression Module 24 and judgment result summary module 25, wherein,

[0043] Server 1 is used to receive the data packet to be verified;

[0044] The network data packet distribution matrix module 21 is used for receiving the data packet to be verified from the server;

[0045] The regular expression module 24 is used to obtain the regular expression for verifying the data packet to be verified;

[0046] The data packet micro-kernel judging module 22 is used to execute the regular expression to verify...

no. 2 example

[0055] figure 2 It is a flow chart of the data packet verification method provided by the second embodiment of the present invention, consisting of figure 2 It can be seen that, in this embodiment, the data packet verification method provided by the present invention includes:

[0056] S201: the server receives the data packet to be verified;

[0057] S202: The FPGA receives the data packet to be verified and the regular expression used to verify the data packet to be verified from the server;

[0058] S203: The FPGA invokes multiple microkernels in parallel to execute regular expressions to verify the data packets to be verified;

[0059] S204: The FPGA combines the inspection results of the micronuclei and sends them to the server.

[0060] In some embodiments, before the method in the foregoing embodiment calls a plurality of microkernels in parallel, the FPGA also includes: the FPGA obtains all values ​​of the data packet to be verified, and calls a corresponding number...

no. 3 example

[0073] For regular expressions based on software implementation, instructions are executed in a serial order, and it is difficult to further improve the detection speed. This embodiment provides a new verification system, such as image 3 As shown, the FPGA-based hardware is integrated into the server system with the PCIE bus, reads data and regular expression algorithms from the server according to the instructions of the server, and realizes parallel regular expression verification by instantiating multiple data packet microprocessing cores in parallel. Upload the final test results to the server. This product uses a regular expression algorithm system based on FPGA hardware. First, FPGA uses a function similar to DMA to share the server's processing of network data packets. Secondly, the parallel regular expression algorithm based on FPGA realizes algorithm acceleration in a shorter cycle. Supports high-speed real-time data packet inspection. Finally, FPGA can instantiate ...

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Abstract

The invention provides a data packet verification method and a data packet verification system. The data packet verification method comprises the steps of receiving a to-be-verified data packet by a server; receiving the to-be-verified data packet and a regular expression for verifying the to-be-verified data packet from the server by the FPGA; parallelly calling a plurality of micro-kernels for executing the regular expression by the FPGA and verifying the to-be-verified data packet; combining verification results of the micro-kernels by the FPGA and transmitting a combined verification result to the server. A parallel regular expression algorithm which is realized based on the FPGA realizes algorithm acceleration in a shorter period and supports high-speed real-time data packet checking. The FPGA can simultaneously and parallelly call a plurality of algorithm operation kernels according to the requirement, thereby realizing algorithm improvement by times.

Description

technical field [0001] The invention relates to the field of information security, in particular to a data packet verification method and system. Background technique [0002] In order to ensure the security of information, the existing technology provides a variety of verification methods. Among them, regular expressions have become a software tool language for network data detection and identification because of its special data processing characteristics. [0003] On the server, the software-based regular expressions execute instructions in a serial manner. Today, with the development and popularization of the Internet, it is becoming more and more difficult for the server to check massive network data packets, and it is difficult to further improve the detection speed. Contents of the invention [0004] The invention provides a data packet verification method and system to provide a new data packet verification method. [0005] The invention provides a data packet ver...

Claims

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Application Information

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Patent Type & Authority Applications(China)
IPC IPC(8): H04L9/32
CPCH04L9/32H04L2209/125
Inventor 乔汉志
Owner SHENZHEN PANGO MICROSYST CO LTD
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