Semiconductor wafer test method, projection manufacturing method, semiconductor device and electronic device

Abstract

The invention provides a semiconductor wafer test method, and a wafer projection manufacturing method, a semiconductor device and an electronic device and relates to the technical field of a semiconductor. The semiconductor wafer test method comprises a step that during a probe test, test probe mark is made to deviate from the center position of a welding pad. The wafer projection manufacturing method comprises steps that during the probe test, the test probe mark is made to deviate from the center position of the welding pad, is utilized at a welding pad opening forming a wafer projection and is arranged at a region not influenced by the test probe mark. The semiconductor wafer test method and the wafer projection manufacturing method are advantaged in that influence of the test probe mark on manufacturing a ball bottom metal layer in the projection process can be completely prevented, a defect of projection missing can be avoided, packaging reliability is improved, and the packaging yield is further improved. The semiconductor device and the electronic device employing the semiconductor wafer test method and the wafer projection manufacturing method have similar advantages.

Description

technical field [0001] The present invention relates to the field of semiconductor technology, in particular to a semiconductor wafer testing method, a wafer bump manufacturing method, a semiconductor device formed by using the semiconductor wafer testing and bump manufacturing method, and a semiconductor device having the semiconductor device electronic device. Background technique [0002] With the development of portable and high-performance microelectronic products in the direction of shortness, smallness, lightness, and thinning, the traditional wire bonding method (Wire Bonding) as a packaging technology for combining chips with various substrates can no longer meet the needs of current consumer electronics products. Demand, replaced by bump packaging has become the key technology of wafer-level packaging. However, the manufacturing process of high-end chips is very complicated and the yield rate is difficult to control, while the yield rate of the bump manufacturing ...

AI Technical Summary

Problems solved by technology

However, the manufacturing process of high-end chips is very complicated and the yield rate is difficult to control, while the yield rate of the bump manufacturing process is relatively stable. Therefore, in order to save packaging costs, it is usually necessary to perform chip probe testing (CP, chip probing) to screen the wafers and pick out unqualified chips

But when doing CP testing, the probes will come into contact with the pads of the wafer, which may cause damage or contamination of the pads (such as aluminum pads)

At the same time, the test pin marks make the surface of the pad uneven, which makes it difficult to use physical vapor deposition to prepare the bottom metal layer in the subsequent bumping process

The quality of the metal layer at the bottom of the ball has a great impact on the subsequent bumping process, such as figure 1 As shown, the middle part of the aluminum pad in area 100 in the figure is the defect on the surface of the aluminum pad caused by the test needle mark, which makes the surface of the pad uneven, and the metal layer at the bottom of the ball is not deposited well, resulting in missing bumps.

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