Semiconductor packaging part and manufacturing method therefor

Abstract

The invention provides a semiconductor packaging part and a manufacturing method therefor. The semiconductor packaging part comprises a substrate, a dielectric layer, a rewiring structure, a semiconductor chip, and an encapsulating layer, wherein the substrate comprises a first surface, a second surface back to the first surface, and conductive columns which extend in the substrate to connect the first surface and the second surface; the dielectric layer is positioned on the first surface of the substrate; the rewiring structure is arranged in the dielectric layer and electrically connected to the conductive columns; the semiconductor chip is arranged on the dielectric layer and electrically connected to the rewiring structure; and the encapsulating layer is positioned on the dielectric layer and encapsulates the semiconductor chip, wherein each of the substrate and the encapsulating layer is formed by a moulding material.

Description

technical field [0001] The invention relates to the field of semiconductor packages, in particular to a semiconductor package for preventing warping and a manufacturing method thereof. Background technique [0002] With the rapid popularization of electronic products such as mobile phones, tablet computers, and digital cameras, semiconductor packages are being used more and more widely. Generally, a flip chip ball grid array (Flip-Chip Ball Grid Array, FCBGA) semiconductor package is a typical package structure. In the package structure, an active surface of at least one semiconductor chip may be electrically connected to one surface of the substrate via a plurality of conductive bumps. An underfill is filled between the semiconductor chip and the substrate so that the underfill of the semiconductor chip surrounds the conductive bumps and fills spaces between the conductive bumps to enhance the strength of the conductive bumps and support the semiconductor chip. Meanwhile,...

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Problems solved by technology

[0005] However, although this design can reduce the warpage of the semiconductor package, because the thickness of the redistribution structure of the semiconductor package is limited, the ability to balance the warpage through the compressive stress layer arranged in the redistribution structure is limited, and it does not Enables precise control of warpage defects produced by epoxy molding compounds (EMC)

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