Convex point structure of semiconductor wafer

Abstract

The invention provides a convex point structure of a semiconductor wafer. The convex point structure comprises a wafer, a regenerative passivation layer formed on the upper surface of the wafer, a polymer material layer formed on the lower surface of the wafer and back adhesive layers formed on all exposed surfaces of the polymer material layer. Compared with the prior art, the forming method for the convex point structure of the semiconductor wafer, provided by the invention, has the advantages that the wafer warppage can be reduced, and thus, the fabrication of processes such as test, printing and ball implantation before cutting is facilitated.

Description

technical field [0001] The invention relates to the technical field of semiconductors, in particular to a semiconductor wafer bump structure. Background technique [0002] In recent years, under the joint promotion of the cost reduction and the improvement of the front-end wafer manufacturing process of semiconductor devices, the single chip size of semiconductor devices with the same function has become smaller and smaller, and can be formed directly on the semiconductor wafer. Ball bumps mounted on printed circuit boards can be applied. Due to the limitations of the semiconductor wafer manufacturing process or the designer's consideration of multiple uses of the same integrated circuit, it is necessary to redefine the position of the input terminal for transmitting electrical signals to form a ball bump during semiconductor wafer level packaging, which requires metal rewiring structure. However, when the thickness of the rewiring metal layer of the semiconductor wafer bu...

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Problems solved by technology

However, when the thickness of the rewiring metal layer of the semiconductor wafer bump structure exceeds 10um, it is easy to form warpage during the packaging process, and the warpage degree is above 2mm, and can even reach 4mm, which cannot realize the large-scale manufacturing of semiconductor wafer level packaging. Production requirements; at the same time, it is easy to form a delamination between the bottom of the re-engineered passivation layer and the top of the re-wiring metal layer during the subsequent deterioration test, and this product is likely to cause subsequent electrical performance failure; in addition, for high-speed dedicated semiconductor devices Although this packaging structure meets the requirements of the flip-chip packaging structure structurally, it does not avoid the semiconductor device failure caused by the influence of α-rays in the metal solder on the circuit in the semiconductor chip to the greatest extent.

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