Formation method for fin type semiconductor device

Abstract

Disclosed is a formation method for a fin type semiconductor device. The formation method comprises the steps of providing a substrate which comprises a circuit region and a storage region, wherein fin parts are arranged on the surface of the substrate in the circuit region and the storage region; forming an isolation layer on the surface of the substrate, wherein the surface of the isolation layer is lower than the top surfaces of the fin parts; forming a dielectric layer on the isolation layer and the surfaces of the fin parts, wherein a first trench which transversely crosses the fin parts is formed in a dielectric layer of the storage region; the first trench exposes a part of side walls and top surfaces of the fin parts in the storage region; a second trench which transversely crosses the fin parts is formed in a dielectric layer of the circuit region; and the second trench exposes a part of side walls and top parts of the fin parts in the circuit region; forming a first gate dielectric layer on the side walls and the top parts of the fin parts at the bottom of the first trench; forming a second gate dielectric layer on the side walls and the top parts of the fin parts at the bottom of the second trench, and on the surface of the first gate dielectric layer; and then forming a first gate in the first trench and forming a second gate in the second trench. By virtue of the formation method, the leakage current in the fin type semiconductor device can be reduced while the stability of the fin type semiconductor device can be improved.

Description

technical field [0001] The present invention relates to the technical field of semiconductor manufacturing, and in particular, to a method for forming a fin-type semiconductor device. Background technique [0002] As a member of the memory, Static Random Access Memory (SRAM) has the advantages of high speed, low power consumption and compatibility with standard processes, and is widely used in computers, personal communications, consumer electronics (smart cards, digital cameras, multimedia players) and other fields. [0003] figure 1 It is a schematic diagram of the circuit structure of the memory cell of the existing 6T (Transistor, transistor) structure of the static random access memory, including: a first PMOS transistor P1, a second PMOS transistor P2, a first NMOS transistor N1, a second NMOS transistor N2, a third NMOS transistor N3 and fourth NMOS transistor N4. The first PMOS transistor P1, the second PMOS transistor P2, the first NMOS transistor N1, and the sec...

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Problems solved by technology

[0006] However, as the device density in the SRAM increases and the size shrinks, the performance of the SRAM composed of FinFETs also decreases.

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