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LDMOS device

A device and conductivity type technology, applied in the direction of semiconductor devices, electrical components, circuits, etc., can solve the problems of inability to deplete and affect the on-resistance of the device, and achieve the effect of low on-resistance, improved high-voltage resistance, and increased width.

Active Publication Date: 2017-07-21
CSMC TECH FAB2 CO LTD
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  • Summary
  • Abstract
  • Description
  • Claims
  • Application Information

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Problems solved by technology

However, its structure has certain disadvantages: there will be a certain length of JFET area at the source end. If the width of this area is small, the current path will be limited, which will affect the on-resistance of the device; if the sub-area is large, the device will respond to withstand voltage. Due to the high concentration of N-type impurities in the drift region, it cannot be depleted

Method used

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Embodiment Construction

[0030] In the following description, numerous specific details are given in order to provide a more thorough understanding of the present invention. It will be apparent, however, to one skilled in the art that the present invention may be practiced without one or more of these details. In other examples, some technical features known in the art are not described in order to avoid confusion with the present invention.

[0031] It should be understood that the invention can be embodied in different forms and should not be construed as limited to the embodiments set forth herein. Rather, these embodiments are provided so that this disclosure will be thorough and complete, and will fully convey the scope of the invention to those skilled in the art. In the drawings, the size and relative sizes of layers and regions may be exaggerated for clarity. Like reference numerals refer to like elements throughout.

[0032] It will be understood that when an element or layer is referred t...

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Abstract

The invention provides an LDMOS device, and relates to the technical field of semiconductors. The LDMOS device includes a substrate having a first conduction type; a first drift region located in the substrate and having a second conduction type; a first well region located in the substrate and adjacent to the first drift region at an interval in the substrate and having the first conduction type; an epitaxial layer located on the substrate and including a second drift region having the second conduction type, and a second well region having the first conduction type and a doping region having the second conduction type which are located at two sides of the second drift region respectively, the second well region being located on the first well region; and a first buried layer located in the first drift region and the second drift region and having the first conduction type. The structure of the LDMOS device optimizes a JFET region of a source end, increases the width of a current path, obtains lower on resistance while obtaining high breakdown voltage, and realizes a multi-layer RESURF structure.

Description

technical field [0001] The invention relates to the technical field of semiconductors, in particular to an LDMOS device. Background technique [0002] Laterally Diffused Metal Oxide Semiconductor (LDMOS for short) devices are widely used in smart power integrated circuits because of their high-voltage withstand characteristics. Off-state high voltage resistance and on-resistance are important indicators to characterize the characteristics of LDMOS devices, and they are also a pair of contradictions faced in the process of device manufacturing. In order to further improve the characteristics of the device and solve the contradictions faced, the concept of LDMOS device with reduced surface field (RESURF=Reduced Surface Field) has been introduced and widely used. [0003] figure 1 A schematic cross-sectional view of a conventional three-layer RESURF LDMOS is shown. It includes: a P-type substrate 101, a P-type deep well 102 located in the P-type substrate 101 and an N-type d...

Claims

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Application Information

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IPC IPC(8): H01L29/06H01L29/78
CPCH01L29/0623H01L29/0634H01L29/7816H01L29/42368H01L29/7835H01L29/1041H01L29/1083
Inventor 张广胜张森
Owner CSMC TECH FAB2 CO LTD
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