Check point technology-based dual pipeline and fault tolerance method

Abstract

The invention discloses a check point technology-based dual pipeline and a fault tolerance method. The check point technology-based dual pipeline is characterized by comprising a pipeline A, a pipeline B, an instruction cache (301), a backup register group (401), comparison logic (501), a write cache (601), a data cache (701) and a register file (801). According to the check point technology-based dual pipeline, contents of interstage registers of the pipelines are backed up by adopting backup registers; single event faults in pipeline units are detected through the comparison logic; and by utilizing a method for recovering the pipelines by values in the backup register group, fault tolerance is performed on SEU, SET and MBU faults caused by single event effects.

Description

technical field [0001] The invention relates to a detection and recovery device for pipeline errors of a microprocessor, in particular to a detection and recovery device for pipeline errors in a SPARC V8 processor. The invention also relates to a method for shielding data reversal errors in pipelines in a SPARC V8 processor. Background technique [0002] Single event upset (Single Event Upset, SEU) is an event in the space application environment, due to the incident of a single event, the data flip error occurs in the storage unit of the integrated circuit, and it is one of the important causes of electronic system failure and abnormal operation in the space environment. . With the rapid development of semiconductor process technology, the size of the chip is continuously reduced, the operating frequency of the processor is continuously increased, and the reduction of the operating voltage of the node makes the single event upset phenomenon more and more serious. A single...

AI Technical Summary

Problems solved by technology

[0004] The existing reinforcement technology for space microprocessors has the following three schemes: the time-based fault-tolerant method can effectively solve the MBU problem, but the processor performance is greatly reduced; the code-based fault-tolerant method can only effectively verify the calculation part Correctness, and different encoding methods cannot handle all single event faults, and the fault tolerance is limited; using a hardware-based redundancy scheme, register-level triple-mode redundancy cannot cope with MBU faults; pipeline-level triple-mode redundancy , although the faulty pipeline can be located, but the overhead of hardware resources and power consumption is high; pipeline-level dual-mode redundancy can deal with MBU failures, but it cannot be located and cannot shield the faults, and the pipeline rollback will increase significantly every time Pipelining performance overhead, especially as single event faults are increasingly common, can significantly slow down overall processing

Self-recovery dual redundant pipeline (Self-Recovery Dual Pipeline, SRDP) on the basis of dual redundant pipeline, through comparison logic to detect faults, self-check logic to locate faults, to realize the execution of errors caused by SET, SEU, MBU faults , although SRDP has a good fault-tolerant effect on single event faults, the serialization of comparison logic and functional logic, self-checking coding logic, and complex pipeline recovery operations lead to a large decrease in the main frequency of the processor

In short, the existing technology cannot implement a CPU hardening solution with low area, low performance overhead and effective response to SEU, SET and MBU faults

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