Coated chip dimension packaging structure and packaging method thereof

Abstract

The present invention discloses a coated chip dimension packaging structure and a packaging method thereof, belonging to the semiconductor packaging technology field. A passivation layer (210) is arranged at the right surface of a silicon-based body (111), a chip electrode (113) is embedded into the right side of the silicon-based body (111) from the back, the upper surface of the passivation layer (210) is provided with a dielectric layer I (310), the edge of the passivation layer (210) is not coated with the dielectric layer I (310), the passivation layer (210) is coated with a metal seed layer I (410), a metal layer I (510) and a dielectric layer II (320), and the dielectric layer II (320) is provided with a dielectric layer II opening I (321) exposed out of the upper surface of a metal layer I (510); and the upper surface of the metal layer I (510) is provided with a bump bottom metal II, an encapsulated layer II (123) is arranged around the silicon-based body (111) and at the back surface of the silicon-based body (111), and the encapsulated layer II (123) is extended upwards to wrap the exposure portion of the passivation layer (210) so as to realize that insulation protection side walls can be performed and the leakage or short circuit is not easy so as to avoid photoetching offset caused by chip offset.

Description

technical field [0001] The invention relates to an encapsulating chip size packaging structure and a packaging method thereof, belonging to the technical field of semiconductor packaging. Background technique [0002] With the increase of wireless handheld devices, palmtop computers and other mobile electronic devices, consumers' demand for various products with small appearance and rich features is also increasing day by day. , miniaturization and low cost" development trend brings challenges and opportunities. Wafer-level chip size packaging technology meets the requirements of electronic products for smaller, more functional, and higher reliability circuit components. However, wafer-level chip size packaging also faces some problems. As the chip becomes smaller and thinner, and its sidewall is not protected, the pick-and-place of the chip during SMT will cause corner stress and even chip fragmentation. [0003] At the same time, in the traditional fan-out chip size pack...

AI Technical Summary

Problems solved by technology

However, wafer-level chip size packaging also faces some problems. As the chip becomes smaller and thinner, and its side wall is not protected, the pick-and-place of the chip during SMT will cause edge stress and even chip fragmentation.

[0003] At the same time, in the traditional fan-out chip size packaging process, the reconstituted wafer is then subjected to the RDL process, which often has the problem of lithography offset caused by chip offset.

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