FPGA logic testing structure and method

Abstract

The invention discloses an FPGA logic testing structure and method. The FPGA logic testing structure includes an FPGA module, an external storage module and a control module, wherein the FPGA module provides internal signals to be tested or variables of the FPGA; the external storage module is connected with the FPGA module and performs storage processing on the internal signals to be tested or variables of the FPGA module; and the control module is connected with the external storage module, selects the stored signals to be tested or variables, completes external reading, determines the internal logic running state of the FPGA module and then displays the internal logic running state of the FPGA module. Compared with the prior art, the FPGA logic testing structure and method can conveniently and efficiently track and observe the signals to be tested, can verify internal logic of FPGA, can greatly improve the efficiency of the initial stage and debugging stage of the project, are low in occupancy of resources, can reduce the development cost relative to a special instrument, have high practicability, are wide in the application range, and are easy for popularization.

Description

technical field [0001] The invention relates to the technical field of FPGA logic testing, in particular to an FPGA logic testing structure and method capable of rapidly locating problems. Background technique [0002] FPGA (Field Programmable Gate Array) is a semiconductor IC that completes circuit design with hardware description language (Verilog or VHDL). After simple synthesis and layout, it is quickly burned to FPGA for testing and can be used for various functional digital Circuit development can also be used for modern IC design verification. [0003] In the development process, it is necessary to test and verify the circuit logic function described by the hardware description language. Generally, the on-chip logic analysis function provided by the FPGA manufacturer can be used, or the logic test and verification can be carried out by using a dedicated logic analysis instrument. However, these methods may take up An uncertain amount of FPGA internal logic resources ...

AI Technical Summary

Problems solved by technology

[0003] In the development process, it is necessary to test and verify the circuit logic function described by the hardware description language. Generally, the on-chip logic analysis function provided by the FPGA manufacturer can be used, or the logic test and verification can be carried out by using a dedicated logic analysis instrument. However, these methods may take up An uncertain amount of FPGA internal logic resources, or high cost, is not conducive to general FPGA project debugging. When FPGA internal signals or variables are abnormal and need to be tested and verified, it is often impossible to quickly locate the problem.

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