LTCC-based CGA integrated packaging structure and realization method thereof

Abstract

The invention discloses an LTCC-based CGA integrated packaging structure and a realization method thereof. An LTCC technology and a CGA technology are combined, and a CGA array is manufactured on the bottom surface of an LTCC substrate by adopting a tool through a welding mode; the LTCC is used as an interconnecting substrate, a packaging body and a passive element integrated carrier of the module at the same time; and the whole region or a partial region on the substrate is welded with a metal surrounding frame, and airtight packaging in the metal surrounding frame region can be realized through parallel seam welding or laser melting seaming ways. The packaging structure is mainly used for the field of system integration as a packaging platform; by adoption of the CGA, high-reliability interconnection between the module and the exterior is realized, so that large module packaging dimensions can be realized; by adoption of the LTCC, integration of active devices and passive elements can be realized at the same time, so that system integrated density is greatly improved; by virtue of the high-precision welding of the metal surrounding frame, high packaging efficiency is realized; due to the position and shape changes of the metal surrounding frame, different applications of electromagnetic shielding, airtightness and the like can be realized; and in addition, the packaging structure has high fundamentality and expandability.

Description

technical field [0001] The invention relates to an LTCC-based CGA integrated packaging structure and a realization method thereof, and belongs to the field of system integrated packaging of electronic products. Background technique [0002] The current main structure of the digital processing circuit is to assemble the discrete packaged chips on the PCB board using SMT technology. However, with the requirements of miniaturization, light weight and high reliability of the product, the conventional process installation method has been difficult to meet the product requirements. [0003] Secondary integration of multiple bare chips or chip-level packaged chips, packaging multiple VLSI (bare chips) and passive components into one package at one time, can greatly reduce the system volume and improve the system performance. reliability, simplify thermal design of the system, and simplify PCB assembly. [0004] The currently commonly used packaging structure is the HTCC integrated...

AI Technical Summary

Problems solved by technology

The packaging structure has the following defects: passive components cannot be integrated, and the system integration density is low; HTCC line resistance is large, and the signal voltage drop is large; HTCC material properties cannot be applied to high frequency fields; HTCC shrinkage consistency is poor, as To ensure good welding of the metal frame, a large edge space needs to be left, and the sidewall width increases with the increase in size, resulting in low packaging efficiency

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