GGNMOS (grounded gate n-channel metal oxide semiconductor) transistor, multi-finger GGNMOS device and circuit

Abstract

The present invention provides a GGNMOS (grounded gate n-channel metal oxide semiconductor) transistor, a multi-finger GGNMOS device and a circuit. A P-type ion implantation region is suspended in the drain region of the GGNMOS transistor; and at least all side surfaces and bottom surface of the P-type ion implantation region are wrapped by the drain region. According to the multi-finger GGNMOS device, P-type ion implantation regions are suspended in the drain terminals of each of GGNMOS transistors; the suspended P-type ion implantation regions form drain regions and lateral Zener auxiliary breakdown regions of a P-type substrate, and therefore, breakdown voltage is low; no PN junctions are formed at the interfaces of the drain regions and the P-type substrate, and therefore, the triggering voltage of ESD (electro-static discharge) protection can be reduced, leakage current introduced by traditional ESD ion implantation can be also reduced, and the reliability of the ESD protection circuit can be improved.

Description

technical field [0001] The invention relates to the technical field of electrostatic discharge protection design of integrated circuits, in particular to a GGNMOS transistor, a multi-finger GGNMOS device and an electrostatic protection circuit. Background technique [0002] In Integrated Circuits (IC), the impact of Electrostatic discharge (ESD) on chip reliability cannot be ignored, especially in today's widespread application of deep submicron and nanotechnology, the external environment, human body, machinery, and radiation fields ESD has a more significant destructive impact on IC chips. The industry has done a lot of research and practice on ESD protection in the process of IC design and manufacturing. Usually, the design of the ESD protection device on the chip needs to consider two aspects: one is that the ESD protection device must be able to discharge a large current; The second is that the ESD protection device should be able to clamp the chip pin terminal voltage...

AI Technical Summary

Problems solved by technology

Although this ESD injection technology can reduce the turn-on voltage of the GGNMOS ESD protection device, it must add a layer of photolithography and implantation process, which increases the manufacturing cost. At the same time, the introduction of the ESD injection brings a larger PN to the device. junction leakage

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