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Bit structure of multi-state magnetic memory

A magnetic memory and magnetic tunnel junction technology, which is applied in the field of non-volatile memory and semiconductor, can solve the problems that the size of the triode cannot be made too small and the storage density of magnetic memory is limited, so as to achieve fast reading speed and improve data storage. Density, energy consumption and radiation resistance

Inactive Publication Date: 2017-12-15
CETHIK GRP
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  • Summary
  • Abstract
  • Description
  • Claims
  • Application Information

AI Technical Summary

Problems solved by technology

[0002] The current magnetic memory bit mostly adopts a 1T1R structure in which a triode is connected in series with a magnetic tunnel junction (MTJ) resistor. In order to ensure sufficient switching current and device reliability for the MTJ, the size of the triode usually cannot be made too small. Therefore, The storage density of magnetic memory is limited by the size of the transistor that provides the switching current for the MTJ

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  • Bit structure of multi-state magnetic memory
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  • Bit structure of multi-state magnetic memory

Examples

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Embodiment 1

[0023] Example 1: figure 1 The reference signs are: word line WL, bit line BL, magnetic tunnel junction MTJ, and the switch is a diode; figure 2 The reference signs are: word line WL, bit line BL, magnetic tunnel junction MTJ, and the switch is a CMOS transistor; Figure 3 to Figure 6 Reference numerals are: free magnetic layer FL (Free Layer), pinned magnetic layer PL (Pinned Layer), insulating layer IL (Insulating Layer), magnetic tunnel junction MTJ.

[0024] In this embodiment, the bit structure of the multi-state magnetic memory is as follows figure 1 As shown, it includes a multi-state magnetic memory cell composed of a word line WL, a bit line BL, a magnetic tunnel junction 1MTJ1 and a magnetic tunnel junction 2MTJ2, and a memory cell selection switch composed of a diode. Memory cell selection switches can also use CMOS transistors, such as figure 2 shown. One of the above two structures can be selected.

[0025] Wherein, the magnetization of the magnetic layer...

Embodiment 2

[0027] Embodiment 2: In this embodiment, the bit structure of the multi-state magnetic memory is as figure 1 As shown, it includes a multi-state magnetic memory cell composed of a word line WL, a bit line BL, a magnetic tunnel junction 1MTJ1 and a magnetic tunnel junction 2MTJ2, and a memory cell selection switch composed of a diode. Memory cell selection switches can also use CMOS transistors, such as figure 2 shown. One of the above two structures can be selected.

[0028] Wherein, the magnetization of the magnetic layers of MTJ1 and MTJ2 is magnetized horizontally or vertically along the in-plane direction, and the positions of the pinned layers of MTJ1 and MTJ2 are different, one pinned layer is at the bottom, and the other pinned layer is at the top. The pinning directions of the pinned layers of MTJ1 and MTJ2 are the same.

[0029] In this embodiment, the multi-state magnetic tunnel junction memory cell such as Figure 4 As shown, two MTJs are interconnected by wire...

Embodiment 3

[0030] Embodiment 3: In this embodiment, the bit structure of the multi-state magnetic memory is as figure 1 As shown, it includes a multi-state magnetic memory cell composed of a word line WL, a bit line BL, a magnetic tunnel junction 1MTJ1 and a magnetic tunnel junction 2MTJ2, and a memory cell selection switch composed of a diode. Memory cell selection switches can also use CMOS transistors, such as figure 2 shown. One of the above two structures can be selected.

[0031] Wherein, the magnetization of the magnetic layers of MTJ1 and MTJ2 is magnetized horizontally or vertically along the in-plane direction, and the positions of the pinned layers of MTJ1 and MTJ2 are different, one pinned layer is at the bottom, and the other pinned layer is at the top. The pinning directions of the pinned layers of MTJ1 and MTJ2 are the same.

[0032] In this embodiment, the multi-state magnetic tunnel junction memory cell such as Figure 5 As shown, two MTJs are interconnected by wire...

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Abstract

The invention relates to a bit structure of a multi-state magnetic memory. The bit structure of the memory comprises a multi-state magnetic tunnel junction memory unit array and a switch circuit composed of a word line, a bit line and a switching device. The bit structure of the multi-state magnetic memory has the advantages of fast reading speed, unlimited number of erasure, low energy consumption and radiation resistance belonging to the magnetic random access memory (MRAM). The multi-state magnetic memory realizes reprogramming only under magnetic field aid, has high safety and can be used as an ideal high-safety multi-programming memory. The multi-state magnetic tunnel junction memory unit is in a multi-resistance state and each memory unit can record 3 or 4 bits of information so that the data storage density is effectively improved and the chip area is reduced. The memory bit can be used for microprocessors and digital circuits with high requirements on characteristics such as high safety, fast reading speed, low power consumption and resistance to radiation and harsh environments.

Description

technical field [0001] The invention relates to the field of non-volatile memory and semiconductor, in particular to a bit structure of multi-state magnetic memory. Background technique [0002] The current magnetic memory bit mostly adopts a 1T1R structure in which a triode is connected in series with a magnetic tunnel junction (MTJ) resistor. In order to ensure sufficient switching current and device reliability for the MTJ, the size of the triode usually cannot be made too small. Therefore, The storage density of magnetic memory is limited by the size of the transistor that provides the switching current for the MTJ. Contents of the invention [0003] In order to overcome the above disadvantages, the present invention aims to provide a bit structure of a multi-state magnetic memory, which can effectively increase the information storage density of the magnetic memory. Based on the principle of magnetic random access memory, the present invention proposes a bit of a mul...

Claims

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Application Information

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Patent Type & Authority Applications(China)
IPC IPC(8): G11C11/56
CPCG11C11/56
Inventor 李辉辉孟皓刘鲁萍刘少鹏戴强刘波
Owner CETHIK GRP
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