Supercharge Your Innovation With Domain-Expert AI Agents!

EEPROM unit simulation model and EEPROM array simulation model

A simulation model, delay unit technology, applied in special data processing applications, instruments, electrical digital data processing, etc., can solve problems such as poor coherence

Active Publication Date: 2017-12-29
SEMICON MFG INT TIANJIN +1
View PDF4 Cites 2 Cited by
  • Summary
  • Abstract
  • Description
  • Claims
  • Application Information

AI Technical Summary

Problems solved by technology

However, when the EEPROM unit simulation model of the prior art is used for full-chip simulation verification, the functional timing verification and data verification need to be performed separately, and the consistency is poor.

Method used

the structure of the environmentally friendly knitted fabric provided by the present invention; figure 2 Flow chart of the yarn wrapping machine for environmentally friendly knitted fabrics and storage devices; image 3 Is the parameter map of the yarn covering machine
View more

Image

Smart Image Click on the blue labels to locate them in the text.
Viewing Examples
Smart Image
  • EEPROM unit simulation model and EEPROM array simulation model
  • EEPROM unit simulation model and EEPROM array simulation model
  • EEPROM unit simulation model and EEPROM array simulation model

Examples

Experimental program
Comparison scheme
Effect test

Embodiment Construction

[0040] When the EEPROM unit simulation model in the prior art is used for full-chip simulation verification, functional timing verification and data verification need to be performed separately. The inventor found out from the research of the prior art that there are two types of single-pipe netlist definitions in the existing EEPROM unit simulation model, namely P type and E type, corresponding to 0 unit and 1 unit. When performing full-chip simulation verification, because the storage unit cannot automatically change the internal storage data according to changes in voltage and external input signals, the two are often verified separately and are not completely covered in the same simulation process. When performing functional timing verification of functional modules, usually only focus on the logic changes of internal important signals, and temporarily ignore the feedback to the data unit, but when performing data verification, the opposite is true. Therefore, functional t...

the structure of the environmentally friendly knitted fabric provided by the present invention; figure 2 Flow chart of the yarn wrapping machine for environmentally friendly knitted fabrics and storage devices; image 3 Is the parameter map of the yarn covering machine
Login to View More

PUM

No PUM Login to View More

Abstract

The invention discloses an EEPROM unit simulation model. The EEPROM unit simulation model comprises a state judgment unit and a variable resistance unit, wherein the state judgment unit is connected with a bit line, a word line and a gate line and outputs a control signal according to input voltage of the bit line, input voltage of the word line and input voltage of the gate line; and one end of the variable resistance unit is connected with the bit line, the other end of the variable resistance unit is connected with a source line, the variable resistance unit receives the control signal, and the resistance value of the variable resistance unit is adjusted according to the control signal. The invention furthermore discloses an EEPROM array simulation model. Through the EEPROM unit simulation model, function time sequence verification and data verification can be performed at the same time.

Description

technical field [0001] The invention relates to the technical field of semiconductor manufacturing, in particular to an EEPROM unit simulation model and an EEPROM array simulation model. Background technique [0002] Electrically Erasable Programmable Read Only Memory (Electrically Erasable Programmable Read Only Memory, EEPROM) is an electrically erasable semiconductor storage device with byte as the minimum modification unit. In the process of developing, designing and debugging EEPROM, it is necessary to simulate and verify the function of EEPROM. The simulation verification of the EEPROM function can be carried out by using the EEPROM unit simulation model (that is, the virtual EEPROM) that can replace the actual EEPROM hardware function. Specifically, it can generate a test code (testbench) and use simulation software (such as NC_verilog software or modelsim software) to accomplish. [0003] In the prior art, the EEPROM cell simulation model is completely established ...

Claims

the structure of the environmentally friendly knitted fabric provided by the present invention; figure 2 Flow chart of the yarn wrapping machine for environmentally friendly knitted fabrics and storage devices; image 3 Is the parameter map of the yarn covering machine
Login to View More

Application Information

Patent Timeline
no application Login to View More
IPC IPC(8): G06F17/50
CPCG06F30/367
Inventor 赵子鉴郑晓程昱许家铭
Owner SEMICON MFG INT TIANJIN
Features
  • R&D
  • Intellectual Property
  • Life Sciences
  • Materials
  • Tech Scout
Why Patsnap Eureka
  • Unparalleled Data Quality
  • Higher Quality Content
  • 60% Fewer Hallucinations
Social media
Patsnap Eureka Blog
Learn More

Browse by: Latest US Patents, China's latest patents, Technical Efficacy Thesaurus, Application Domain, Technology Topic, Popular Technical Reports.

© 2025 PatSnap. All rights reserved.Legal|Privacy policy|Modern Slavery Act Transparency Statement|Sitemap|About US| Contact US: help@patsnap.com