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eeprom unit simulation model and eeprom array simulation model

A technology of simulation model and comparison unit, which is applied in the direction of instrumentation, calculation, electrical digital data processing, etc., and can solve problems such as poor continuity

Active Publication Date: 2021-04-23
SEMICON MFG INT TIANJIN +1
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  • Summary
  • Abstract
  • Description
  • Claims
  • Application Information

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Problems solved by technology

However, when the EEPROM unit simulation model of the prior art is used for full-chip simulation verification, the functional timing verification and data verification need to be performed separately, and the consistency is poor.

Method used

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  • eeprom unit simulation model and eeprom array simulation model
  • eeprom unit simulation model and eeprom array simulation model
  • eeprom unit simulation model and eeprom array simulation model

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Embodiment Construction

[0040] When the EEPROM unit simulation model in the prior art is used for full-chip simulation verification, functional timing verification and data verification need to be performed separately. The inventor found out from the research of the prior art that there are two types of single-pipe netlist definitions in the existing EEPROM unit simulation model, namely P type and E type, corresponding to 0 unit and 1 unit. When performing full-chip simulation verification, because the storage unit cannot automatically change the internal storage data according to changes in voltage and external input signals, the two are often verified separately and are not completely covered in the same simulation process. When performing functional timing verification of functional modules, usually only focus on the logic changes of internal important signals, and temporarily ignore the feedback to the data unit, but when performing data verification, the opposite is true. Therefore, functional t...

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Abstract

The present invention discloses an EEPROM unit simulation model, comprising: a state judging unit connected to a bit line, a word line and a gate line respectively, according to the input voltage of the bit line, the input voltage of the word line and the The input voltage of the gate line, output control signal; variable resistance unit, one end of the variable resistance unit is connected to the bit line, the other end of the variable resistance unit is connected to a source line, the variable resistance unit The resistance unit receives the control signal, and adjusts the resistance value of the variable resistance unit according to the control signal. The invention also discloses an EEPROM array simulation model. The EEPROM unit simulation model provided by the invention can simultaneously perform function sequence verification and data verification.

Description

technical field [0001] The invention relates to the technical field of semiconductor manufacturing, in particular to an EEPROM unit simulation model and an EEPROM array simulation model. Background technique [0002] Electrically Erasable Programmable Read Only Memory (Electrically Erasable Programmable Read Only Memory, EEPROM) is an electrically erasable semiconductor storage device with byte as the minimum modification unit. In the process of developing, designing and debugging EEPROM, it is necessary to simulate and verify the function of EEPROM. The simulation verification of the EEPROM function can be carried out by using the EEPROM unit simulation model (that is, the virtual EEPROM) that can replace the actual EEPROM hardware function. Specifically, it can generate a test code (testbench) and use simulation software (such as NC_verilog software or modelsim software) to accomplish. [0003] In the prior art, the EEPROM cell simulation model is completely established ...

Claims

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Application Information

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Patent Type & Authority Patents(China)
IPC IPC(8): G06F30/3308
CPCG06F30/367
Inventor 赵子鉴郑晓程昱许家铭
Owner SEMICON MFG INT TIANJIN
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