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An Efficient Wideband Digital Array Receiver Channel Based on Delayed Beamforming

A digital array and time-delay technology, applied in diversity/multi-antenna systems, space transmit diversity, electrical components, etc., can solve the problem that the desired broadband beam pattern cannot be formed

Active Publication Date: 2020-05-12
UNIV OF ELECTRONICS SCI & TECH OF CHINA
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  • Abstract
  • Description
  • Claims
  • Application Information

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Problems solved by technology

[0002] Due to the phased array antenna aperture effect and the antenna aperture transit time of the broadband digital array, the desired broadband beam pattern cannot be formed directly by phase weighting. Therefore, a delay-based broadband beamforming method is required

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  • An Efficient Wideband Digital Array Receiver Channel Based on Delayed Beamforming
  • An Efficient Wideband Digital Array Receiver Channel Based on Delayed Beamforming
  • An Efficient Wideband Digital Array Receiver Channel Based on Delayed Beamforming

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Embodiment Construction

[0018] In order to make the purpose, technical solution and advantages of the present invention clearer, the present invention will be further described in detail below in conjunction with the implementation methods and accompanying drawings.

[0019] see image 3 , in the wideband digital array receiving channel structure based on delay beamforming with the number of channels N, including N LNAs, ADC modules, integer times delay modules, NCOs, amplitude-phase weighting modules, and first fractional delay weighting modules ( Corresponding to the I subgrade band) and the second fractional delay weighting module (corresponding to the Q subgrade band), as well as two L+1 sub-filter banks and a decimation module for realizing M-fold decimation. The structure of the L+1 sub-filter bank is as follows Figure 4 As shown, the L+1 filter inputs are filtered by L+1 Farrow sub-filters and then combined to obtain the filter output y(n), and the output ports of the first and second fracti...

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Abstract

The invention discloses a high-efficiency broadband digital array receiving channel based on delay beamforming, which includes N low-noise power amplifiers, a digital-to-analog conversion module, an integer times delay module, a digital control oscillator, an amplitude-phase weighting module, a first and the second fractional delay weighting module, as well as two sub-filter banks and decimation modules, wherein the low-noise power amplifier is connected to the digitally controlled oscillator through the digital-to-analog conversion module and the integer times delay module, and its non-phase output and quadrature output are respectively passed through the same An amplitude-phase weighting module connects the first and the second fractional time-delay weighting module; Merge the outputs of the fractional time-delay weighting modules corresponding to the I and Q paths respectively, and then serve as the input of the two sub-filter banks respectively, and the sub-filter banks The output terminals are respectively connected to an extraction module with the same extraction multiple. In the present invention, each channel shares a sub-filter group to complete the fractional time delay processing, and then the extraction link is rearranged, thereby effectively reducing the consumption of hardware resources of the multiplier and the adder.

Description

technical field [0001] The invention belongs to the technical field of wideband digital arrays, and in particular relates to a wideband digital array receiving channel structure based on delay beamforming. Background technique [0002] Due to the existence of phased array antenna aperture effect and antenna aperture transit time in broadband digital array, the desired broadband beam pattern cannot be formed directly by phase weighting. Therefore, a delay-based broadband beamforming method is required. When using the digital delay method, the traditional broadband digital array receiving channel includes N LNA (low noise power amplifier), ADC (digital-to-analog conversion), NCO (digital control oscillator) and amplitude-phase weighting module, as well as 2N decimation, Integer delay and fractional delay modules, where N (N>2) represents the number of channels, and its structure is as follows figure 1 Shown: The input terminal of LNA is used to input the array to receive s...

Claims

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Application Information

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Patent Type & Authority Patents(China)
IPC IPC(8): H04B7/08H04B7/0408
Inventor 钱璐邹林姜帅龙王灿周云汪学刚
Owner UNIV OF ELECTRONICS SCI & TECH OF CHINA