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Semiconductor device and manufacturing method therefor

A manufacturing method and semiconductor technology, applied in the direction of semiconductor devices, electrical solid devices, electrical components, etc., can solve the problems affecting the device performance, the off-state leakage current of the device and the control of the short channel effect, etc., to improve the line The effect of edge roughness

Active Publication Date: 2018-02-02
YANGTZE MEMORY TECH CO LTD
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  • Summary
  • Abstract
  • Description
  • Claims
  • Application Information

AI Technical Summary

Problems solved by technology

[0006] The LER that appears in the feature will eventually affect the performance of the device. For example, if the LER appears when forming the gate, it will greatly affect the off-state leakage current and the control of the short channel effect of the device.

Method used

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  • Semiconductor device and manufacturing method therefor
  • Semiconductor device and manufacturing method therefor
  • Semiconductor device and manufacturing method therefor

Examples

Experimental program
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Effect test

Embodiment 1

[0042] Such as figure 2 As shown, it is a ladder structure of a 32-layer NAND memory, 50 is a photoresist, 30 is a semiconductor device, and 40 is a ladder structure in a semiconductor device. In this embodiment, the ladder structure is a conductive layer, that is, a multi-layer conductive layer. step shape, the specific manufacturing method of the step in this embodiment is as follows Figure 6 As shown, the etching of the ladder structure is mainly completed through three steps. In the first step, the photoresist coating is applied to the part that needs to be fabricated with a coating machine to form a photoresist layer. In the second step, the photoresist profile is micro-etched. process, the third step is to etch the semiconductor device with the photoresist after the microlithography process as a mask, wherein the photoresist coating will consume the photoresist but hardly consumes the bottom, while the etching consumes the photoresist At the same time, the bottom subs...

Embodiment 2

[0050] Such as image 3 As shown, it is a ladder structure of a 64-layer memory, 50 is a photoresist, 31 is a first division in a semiconductor structure, 32 is a second division in a semiconductor structure, 41 is a ladder structure of a first division, and 42 is a second division. The ladder structure of the partition, in this embodiment, the ladder structure is selected as the array block of the memory, that is, a ladder shape is formed by a plurality of memory array blocks, and there is a height difference between the first partition 31 and the second partition 32 in the vertical direction, so there is The following two problems: (1) gaps are more likely to appear in the contact layer between the photoresist and the bottom substrate during the glue coating process; (2) the uniformity of glue coating on the step etching surface in the horizontal direction becomes worse.

[0051] In the etching process of the stepped structure, the etching of the stepped structure is mainly ...

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Abstract

The invention belongs to the manufacturing technical field of a semiconductor device, and specifically relates to a semiconductor device and a manufacturing method therefor. Along with development ofthe semiconductor device from 32 layers to 64 layers, the problem of line edge roughness becomes severe increasingly. In a stair etching process, the edge outline shape of photoresist is strictly controlled to solve the problem of the step edge roughness; and the stair line edge roughness is improved, so that a processing window of a connecting hole etching critical dimension can be added.

Description

technical field [0001] The invention belongs to the field of semiconductor devices, and more specifically relates to a manufacturing method for reducing edge roughness formed in a semiconductor device and a semiconductor device manufactured by using the manufacturing method. Background technique [0002] As technology develops, the semiconductor industry is constantly looking for ways to produce memory devices with a greater number of memory cells per memory die. In non-volatile memory, such as NAND memory, one way to increase memory density is through Use a vertical memory array, that is, 3D-NAND; as the integration level becomes higher and higher, 3D-NAND has developed from 32 layers to 64 layers, or even higher layers. [0003] In order to achieve a higher integration level, the critical dimension (CD, Critical Dimension) is getting smaller and smaller, and such features include, for example, connection lines and functional areas formed in semiconductor devices. [0004]...

Claims

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Application Information

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Patent Type & Authority Applications(China)
IPC IPC(8): H01L27/11578H01L27/11575H01L27/11551H01L27/11548H10B43/20H10B41/20H10B41/50H10B43/50
CPCH10B41/50H10B41/20H10B43/50H10B43/20
Inventor 胡军赵祥辉曾最新章诗陈保友
Owner YANGTZE MEMORY TECH CO LTD