Electronic stack structure and method for fabricating the same

Abstract

An electronic stack structure is provided, including a first substrate, a second substrate stacked on the first substrate through a plurality of passive elements, and an electronic element disposed onat least one of the first substrate and the second substrate. As such, the distance between the first substrate and the second substrate is defined by the height and size of the passive elements. Thepresent disclosure further provides a method for fabricating the electronic stack structure.

Description

technical field [0001] The present invention relates to a stacking structure, in particular to an electronic stacking structure and its preparation method. Background technique [0002] With the vigorous development of portable electronic products in recent years, all kinds of related products are gradually developing toward the trend of high density, high performance, and light, thin, short, and small. In response to this trend, the semiconductor packaging industry has developed various embodiments. Package on package (PoP for short) technology is expected to meet the requirements of light, thin, small and high density. [0003] like figure 1 As shown in FIG. 1 , it is a schematic cross-sectional view of a conventional packaging stack structure 1 . like figure 1 As shown, the package stack structure 1 includes: a first substrate 11 having opposite first surfaces 11a and second surfaces 11b; a first semiconductor chip 10 flip-chip bonded to the first substrate 11; formed ...

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Problems solved by technology

[0004] However, in the existing packaging stack structure 1, since the first and second substrates 11, 12 use solder pillars 13 as elements for supporting and electrically connecting, with the number of contacts (ie I / O) of electronic products More and more, when the size of the package remains the same, the distance between the solder columns 13 needs to be reduced, resulting in the phenomenon of bridging (bridge), which leads to low product yield and poor reliability. And other problems, making it impossible to apply to more precise fine-pitch products

[0005] In particular, the volume and height tolerance of the solder column 13 after reflow is large, that is, the dimensional variation is difficult to control, so that not only the joints are prone to defects (for example, the solder column 13 will first become soft and collapsed during reflow) At the same time, after bearing the weight of the second substrate 12 above, the solder column 13 is easy to collapse and deform, and then bridges with the adjacent solder column 13), resulting in poor electrical connection quality, and the grid-like arrangement of the solder columns 13 The grid array is prone to poor coplanarity, resulting in unbalanced contact stress, which may easily cause the first substrate 11 and the second substrate 12 to be connected at an angle, and even cause contact offset problems.

[0006] In addition, if copper pillars are used to replace the solder pillars 13 as supports, although the problem of inclined connection can be avoided, the cost of copper pillars is relatively high, so it is not economical.

[0007] Moreover, since the solder columns 13 occupy the layout space of the first substrate 11 and the second substrate 12, it is difficult to increase the number of passive components on the first substrate 11 and the second substrate 12, so the package stack structure 1 It is difficult to meet the requirements of high performance; if the number of chips or passive components is to be increased on the first substrate 11 and the second substrate 12, it is necessary to increase the layout area of ​​the first substrate 11 and the second substrate 12, causing the packaging Stacking structure 1 does not conform to the trend of light, thin, short and small design

[0008] In addition, the ground of passive components (not shown) disposed on the first substrate 11 or the second substrate 12 needs to be connected to the system ground through solder pillars 13, resulting in a too long transmission path. while reducing the electrical characteristics of the package stack structure 1

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