Chip-size wafer-level scale packaged dynamic random access memory and manufacturing method therefor

Abstract

The invention relates to the field of semiconductor packaging, and discloses a chip-size wafer-level scale packaged dynamic random access memory and a manufacturing method therefor. The dynamic randomaccess memory comprises a stacked chip; the stacked chip comprises main chips and a control chip; and the main chips and the control chip are arranged in a stacked manner and the control chip is stacked between the two main chips. By enabling the control chip to be stacked between the two main chips of the stacked chip, particularly in the middle layer position of the stacked chip, the maximum connection distance between each main chip and the control chip can be obviously shortened, thereby effectively accelerating signal transfer between the chips; and meanwhile, the problems of signal noise and heating of the dynamic random access memory can be well controlled conveniently.

Description

technical field [0001] The invention relates to the field of semiconductor packaging, in particular to a chip-sized wafer-level scale packaged dynamic random access memory (DRAM) and a manufacturing method thereof. Background technique [0002] DRAM (Dynamic Random Access Memory) is a common system memory. [0003] Currently used dynamic random access memory, such as figure 1 As shown, it includes a plurality of main chips 1 stacked on each other, a control chip 2 located above the multiple main chips 1, and a ball grid array 3 packaged above the control chip 2, wherein the multiple main chips 1 are connected to each other through silicon vias 5 , multiple main chips 1 and control chips 2 are connected through micro-bumps 4 . Although this kind of dynamic random access memory can greatly improve the storage capacity of the storage device, because the control chip 2 is usually located at the top or bottom of multiple main chips 1, the connection distance between some main c...

AI Technical Summary

Problems solved by technology

Although this kind of dynamic random access memory can greatly improve the storage capacity of the storage device, because the control chip 2 is usually located at the top or bottom of multiple main chips 1, the connection distance between some main chips 1 and the control chips 2 is too long, and The distances between each main chip 1 and the control chip 2 are different, resulting in a signal transmission delay between the main chip 1 and the control chip 2, which greatly increases the power consumption and signal noise of the DRAM, and also causes heat dissipation. The emergence of problems

In addition, the use of the micro-bump 4 will greatly increase the manufacturing cost of the DRAM

[0004] Therefore, it is necessary to provide a dynamic random access memory that can solve the above-mentioned problems such as signal transmission delay, power consumption and signal noise increase, and has low manufacturing cost.

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