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Semiconductor structure forming method

A semiconductor and substrate technology, applied in the field of semiconductor structure formation, can solve problems such as semiconductor performance needs to be improved, and achieve the effects of reducing heating process, suppressing stress release, and suppressing shrinkage

Active Publication Date: 2018-03-09
SEMICON MFG INT (SHANGHAI) CORP +1
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  • Abstract
  • Description
  • Claims
  • Application Information

AI Technical Summary

Problems solved by technology

[0005] However, after the stress layer is introduced in the prior art, the performance of the semiconductor needs to be improved

Method used

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  • Semiconductor structure forming method
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  • Semiconductor structure forming method

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Embodiment Construction

[0034] It can be seen from the background art that the semiconductor structure in the prior art has the problem of poor performance. Now combine a semiconductor structure method to analyze the reasons for its performance problems:

[0035] figure 1 , shows a schematic cross-sectional structure corresponding to each step of a method for forming a semiconductor structure.

[0036] refer to figure 1 , forming a base, the base includes a substrate 10 and discrete fins 11 located on the substrate 10; forming a gate structure 13 on the base, the gate structure 13 spanning the fins 11 and Covering the surface of part of the top and part of the sidewall of the fin 11; forming a stress layer 14 in the fin 11 on both sides of the gate structure 13, and ionizing the stress layer 14 by using an in-situ self-doping process Doping to form source and drain doped regions.

[0037] continue to refer figure 1 , performing annealing treatment 15 to activate dopant ions in the source-drain d...

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Abstract

A semiconductor structure forming method comprises steps: a substrate is formed; a pseudo gate structure is formed; a stress layer is formed; a source and drain doping area is formed; an interlayer dielectric layer is formed; an opening is formed, and the bottom part of the opening exposes an oxidation layer; first annealing processing is carried out to activate doped ions in the source and draindoping area; and during the first annealing processing process, the oxidation layer at the bottom part of the opening is restored. In the technical scheme of the invention, as the interlayer dielectric layer covers the stress layer, the interlayer dielectric layer can thus play a suppression role on the stress layer, the possibility of a melting phenomenon happening to the stress layer during thefirst annealing processing process can be reduced, stress release of the stress layer during the first annealing processing process is suppressed, and contraction of the stress layer during the firstannealing processing process is suppressed. The first annealing processing can activate doped ions in the source and drain doping area and can also restore the exposed oxidation layer, a heating process during the semiconductor structure forming process can thus be reduced, and the performance of the formed semiconductor structure is improved.

Description

technical field [0001] The invention relates to the field of semiconductor manufacturing, in particular to a method for forming a semiconductor structure. Background technique [0002] With the rapid development of semiconductor manufacturing technology, semiconductor devices are developing towards higher element density and higher integration. As the most basic semiconductor device, transistors are currently being widely used. Therefore, with the increase of component density and integration of semiconductor devices, the gate size of planar transistors is getting shorter and shorter. The ability of traditional planar transistors to control channel current Weakened, resulting in short channel effect, resulting in leakage current, and ultimately affecting the electrical performance of semiconductor devices. [0003] In order to overcome the short-channel effect of the transistor and suppress the leakage current, a Fin Field Effect Transistor (Fin FET) is proposed in the prio...

Claims

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Application Information

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IPC IPC(8): H01L21/336H01L21/324
CPCH01L21/324H01L29/66545H01L29/66795
Inventor 周飞
Owner SEMICON MFG INT (SHANGHAI) CORP
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