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Circuit board provided with double reinforcing layers and integrated double route circuits and manufacturing method thereof

A technology of reinforcement layer and circuit board, applied in the direction of circuit, printed circuit components, printed circuit stress/deformation reduction, etc., can solve problems such as no fan-out routing, inability to solve characteristic problems, etc.

Inactive Publication Date: 2018-03-16
BRIDGE SEMICON
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  • Summary
  • Abstract
  • Description
  • Claims
  • Application Information

AI Technical Summary

Problems solved by technology

However, although the circuit board can reduce inductance, it cannot solve other characteristics because it does not have enough fan-out routing capability to meet the high requirements of ultra-dense pitch flip-chip assembly. Issues (e.g. design flexibility)

Method used

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  • Circuit board provided with double reinforcing layers and integrated double route circuits and manufacturing method thereof
  • Circuit board provided with double reinforcing layers and integrated double route circuits and manufacturing method thereof
  • Circuit board provided with double reinforcing layers and integrated double route circuits and manufacturing method thereof

Examples

Experimental program
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Effect test

Embodiment 1

[0055] Figure 1-Figure 18 In the first embodiment of the present invention, a diagram of a manufacturing method of a circuit board, which includes a first reinforcement layer, a first routing circuit, a second routing circuit, a series of vertical connection paths and a second reinforcement layer .

[0056] figure 1 and figure 2 They are respectively a cross-sectional view and a top perspective view of the routing lines 135 formed on the sacrificial carrier 110 , wherein the routing lines 135 are formed by metal deposition and metal patterning processes. In this figure, the sacrificial carrier 110 is a single-layer structure, and the routing lines 135 include bonding pads 138 and stacking pads 139 . The sacrificial carrier 110 is usually made of copper, aluminum, iron, nickel, tin, stainless steel, silicon or other metals or alloys, but any other conductive or non-conductive materials can also be used. The thickness of the sacrificial carrier 110 is preferably in the ran...

Embodiment 2

[0085] Figure 22-Figure 31 It is a diagram of a circuit board manufacturing method for embedding electrical components in the second reinforcement layer in the second embodiment of the present invention.

[0086] For the purpose of brief description, any descriptions in the above-mentioned embodiment 1 that can be used for the same application are incorporated here, and it is not necessary to repeat the same descriptions.

[0087] Figure 22 It is a cross-sectional view of the secondary assembly 10 and the first reinforcing layer 20 placed on the carrier film 30 . The subgroup 10 with Figure 10The structures shown are similar, but the only difference is that the sacrificial carrier 110 in this embodiment is a double-layer structure. The subassembly 10 is located in the through opening 205 of the first reinforcement layer 20 , and the sacrificial carrier 110 is attached to the carrier film 30 . The carrier film 30 is usually an adhesive tape, which can provide a temporary...

Embodiment 3

[0103] Figure 34-Figure 37 It is a diagram of a manufacturing method of a circuit board with a third routing circuit in the third embodiment of the present invention.

[0104] For the purpose of brief description, any descriptions in the above embodiments that can be used for the same application are incorporated here, and the same descriptions do not need to be repeated.

[0105] Figure 34 for Figure 29 A cross-sectional view of the third conductive wire 835 formed on the second strengthening layer 53 of FIG. The third wire 835 is formed by metal deposition and metal patterning processes, and extends laterally on the outer surface of the second reinforcement layer 53 and contacts the vertical connection channel 51 .

[0106] Figure 35 It is a cross-sectional view with a fourth dielectric layer 841 and a fourth blind hole 843, wherein the fourth dielectric layer 841 is located on the second strengthening layer 53 and the fourth conductive line 835, and the fourth blind...

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PUM

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Abstract

A circuit board provided with double reinforcing layers and integrated double route circuits is characterized in that a first route circuit and a second router circuit are arranged in a penetrating opening and outside the penetrating opening of a first reinforcing layer and the second route circuit is provided with a series of perpendicular connection channels surrounding by a second reinforcing layer laterally. Circuit board bending can be avoided due to the mechanical strength of the first reinforcing layer and the mechanical strength of the second reinforcing layer. The perpendicular connection channels can provide electric connection points used for next stage connection. The first route circuit in the penetrating opening of the first reinforcing layer can provide a primary fan-out route while the second route circuit disposed outside the penetrating opening of the first reinforcing layer can provide further fan-out route for the first route circuit and also enables mechanical connection of the first route circuit and the first reinforcing layer.

Description

technical field [0001] The invention relates to a circuit board, in particular to a circuit board with double reinforcement layers and integrated double routing circuits and a manufacturing method thereof. Background technique [0002] The market trend of electronic devices (such as multimedia devices) tends to be faster and thinner. One approach is to interconnect semiconductor chips through coreless substrates, allowing for thinner combined devices and improved signal integrity. US Patent Nos. 7,851,269, 7,902,660, 7,981,728 and 8,227,703 disclose various coreless substrates based on this purpose. However, although the circuit board can reduce inductance, it cannot solve other characteristics because it does not have enough fan-out routing capability to meet the high requirements of ultra-dense pitch flip-chip assembly. issues (such as design flexibility). [0003] For the above reasons and other reasons described below, there is an urgent need to develop a new type of ...

Claims

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Application Information

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Patent Type & Authority Applications(China)
IPC IPC(8): H05K1/02H01L23/498H01L21/48
CPCH01L21/4857H01L23/49822H01L23/49827H05K1/0271H01L2224/16225H01L2224/73204H01L2924/181H01L2924/00012
Inventor 林文强王家忠
Owner BRIDGE SEMICON
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