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An Oxide Filling Method for Cutting Lines of Top Select Gate

A filling method and selection gate technology, applied in semiconductor devices, electrical components, circuits, etc., can solve problems such as defects in the top region, and achieve the effect of avoiding tungsten residue and removal

Active Publication Date: 2019-11-26
YANGTZE MEMORY TECH CO LTD
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  • Abstract
  • Description
  • Claims
  • Application Information

AI Technical Summary

Problems solved by technology

[0013] However, in the above step S6, although atomic layer deposition (ALD) is used for oxide filling, a good filling effect of the top select gate cut trench (Top Select Gate Cut Trench) can be obtained, that is, there is no obvious seam or Void, but the oxide formed by filling in this way has a faster hydrofluoric acid (HF ) Wet etching (Wet Etch) corrosion rate and fluorine-containing gas corrosion rate, so in the subsequent annealing process steps and tungsten gate (W-Gate) formation steps, it is easy to be caused by hydrofluoric acid (HF ) wet etching (Wet Etch) and / or the removal of fluorine-containing gas (Fluorin Outgas), causing the ALD filling oxide 70' to be etched, resulting in butterfly (Disshing) defects in the top area (Top Area), and even Form trench 90 (see Figure 2b ), and the trench 90 is filled with deposited tungsten fill 80 in the subsequent formation step of the tungsten common source (W-ACS) (see Figure 2c ), and in the subsequent tungsten common source (W-ACS) chemical mechanical polishing (CMP), it will also be difficult to remove and become tungsten residue 80’ (W Residue) (see Figure 2d and image 3 ), which directly affects the performance of three-dimensional (3D) flash memory

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  • An Oxide Filling Method for Cutting Lines of Top Select Gate
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  • An Oxide Filling Method for Cutting Lines of Top Select Gate

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Embodiment Construction

[0044] Exemplary embodiments of the present disclosure will be described in more detail below with reference to the accompanying drawings. Although exemplary embodiments of the present disclosure are shown in the drawings, it should be understood that the present disclosure may be embodied in various forms and should not be limited by the embodiments set forth herein. Rather, these embodiments are provided for more thorough understanding of the present disclosure, and to fully convey the scope of the present disclosure to those skilled in the art.

[0045] In the interest of clarity, not all features of an actual implementation are described. In the following description, well-known functions and constructions are not described in detail since they would obscure the invention in unnecessary detail. It should be recognized that in the development of any actual embodiment, numerous implementation details must be worked out to achieve the developer's specific goals, such as chan...

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Abstract

The present invention provides a kind of oxide filling method of top select gate tangent line, by adopting high-density plasma chemical vapor deposition method (HDP-CVD) to fill the oxide material in the top select gate tangent channel, the filled oxide obtained can Effectively resist the harmful etching caused by the removal of fluorine-containing gas during the subsequent tungsten gate formation process, thereby avoiding the formation of etching channels and being filled by tungsten deposition, thus avoiding unnecessary tungsten residues and improving the reliability of the 3D NAND flash memory structure Product performance.

Description

technical field [0001] The present invention relates to the field of semiconductor manufacturing, in particular to a method for manufacturing a 3D NAND flash memory structure, specifically an oxide filling method for a tangential line of a top selection gate that avoids tungsten residues during the formation of subsequent gate lines and tungsten common sources. Background technique [0002] With the development of planar flash memory, the production process of semiconductors has made great progress. However, in recent years, the development of planar flash memory has encountered various challenges: physical limits, existing development technology limits, and storage electron density limits. In this context, in order to solve the difficulties encountered in planar flash memory and pursue lower production costs per unit storage unit, various three-dimensional (3D) flash memory structures have emerged, such as 3D NOR (3D or not) flash memory and 3D NAND (3D NAND) flash memory....

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Application Information

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Patent Type & Authority Patents(China)
IPC IPC(8): H01L27/11578H10B43/20
CPCH10B43/20
Inventor 何佳刘藩东夏志良霍宗亮
Owner YANGTZE MEMORY TECH CO LTD
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