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Skew Insensitive Quadrature Clock Error Correction and Duty Cycle Calibration for High Speed ​​Clocks

A clock error, duty cycle distortion technology, applied in the direction of automatic power control, transforming continuous pulse trains into pulse train devices with required patterns, generating/distributing signals, etc. power and other issues

Active Publication Date: 2021-03-16
XILINX INC
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  • Summary
  • Abstract
  • Description
  • Claims
  • Application Information

AI Technical Summary

Problems solved by technology

Current techniques for correcting distortion of clocks at such frequencies are inefficient because they consume too much power or too much die area, or do not adequately correct for distortion

Method used

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  • Skew Insensitive Quadrature Clock Error Correction and Duty Cycle Calibration for High Speed ​​Clocks
  • Skew Insensitive Quadrature Clock Error Correction and Duty Cycle Calibration for High Speed ​​Clocks
  • Skew Insensitive Quadrature Clock Error Correction and Duty Cycle Calibration for High Speed ​​Clocks

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Embodiment Construction

[0018] Techniques for correcting clock distortion are provided. This technique includes the use of circuits for detecting and correcting duty cycle distortion and quadrature clock phase distortion. Duty cycle distortion refers to the difference from the desired duty cycle (typically 50-50), while quadrature clock phase distortion refers to the difference from the 90 degree phase difference between the I and Q signals. For phase detection, the detection circuit is made simpler and more accurate by using a sampling operation in which device mismatches within the detection circuit are accounted for by sampling the charge associated with an ideal clock signal on the sampling capacitor inside. When phase detection is performed with the detection circuit, the stored charge compensates for the device mismatch, thereby increasing the accuracy of the detection circuit. This sampling operation is also used for duty cycle distortion detection. Specifically, a common mode voltage is ap...

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Abstract

A technique for correcting clock distortion. The technique includes the use of circuits for detecting and correcting for duty cycle distortion and quadrature clock phase distortion. For phase detection, the detection circuit (100) is made simpler and more accurate through the use of a sampling operation in which the charge associated with the ideal clock signal across the sampling capacitor (302) is sampling, the device mismatch within the sampling circuit is accounted for. When phase detection is performed with the detection circuit 100, the stored charge compensates for device mismatch, which improves the accuracy of the detection circuit. The sampling operation is also used for duty cycle distortion detection. Specifically, a common-mode voltage is applied across the sampling capacitors (302), which effectively zeros the voltage differential between the sampling capacitors (302), thereby compensating for possible There are deviations. Feedback algorithms use digital values ​​to correct clock distortion.

Description

technical field [0001] Examples of the present disclosure relate generally to high-speed clocks for integrated circuits, and more particularly, to techniques for compensating for clock distortion in high-speed clocks. Background technique [0002] Circuits, such as digital circuits, operate based on clock signals that control the speed at which circuit units operate. Clock signals are often subject to distortion while being transmitted. Circuitry is typically designed to minimize, correct, or compensate for this distortion so that the level of distortion experienced by the clock signal is within acceptable tolerances. [0003] As the clock frequency increases, the level of distortion present in the clock signal has a greater associated effect on the clock. Certain circuits, such as high-speed data links, operate on clocks with particularly high frequencies, such as 56Gb / s. Current techniques for correcting distortion of clocks at such frequencies are inefficient because t...

Claims

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Application Information

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Patent Type & Authority Patents(China)
IPC IPC(8): G06F1/04H03L7/081H03K5/156
CPCG06F1/04H03K5/1565H03K3/017
Inventor H·赫达亚蒂Y·法兰斯
Owner XILINX INC