Active write-back hierarchical instruction memory structure fault-tolerant method and device

Abstract

The present invention provides a fault-tolerant method and device for a hierarchical instruction memory structure that can be actively written back. The device includes a hierarchical instruction memory, an instruction error correction and detection module, an instruction word register, and an instruction address register; the method includes 1. starting and running the processor; Take out the instruction word data from the instruction memory; 3. The instruction word data is sent to the instruction error correction and detection module; 4. Judging the error correction and error detection result "no error or a correctable error occurs"; Yes, continue to step 5; No, go to step 10; 5. Write the instruction word into the instruction word register; 6. Update the instruction address register; 7. Determine that a correctable error occurs; Yes, continue to step 8; No, turn to step 9; 8. Write the instruction word data back to the hierarchical instruction memory; 9. The processing ends; go to step 2, and process the address of the next instruction; 10. An uncorrectable error occurs in the instruction word data, and the processor hangs. The invention realizes the fault tolerance of the instruction and the instruction memory, and has less hardware cost.

Description

technical field [0001] The invention belongs to the field of microprocessor design, and relates to the design of a highly reliable and high-performance processor fault-tolerant structure, in particular to a fault-tolerant method and device for a hierarchical instruction memory structure that can be actively written back. Background technique [0002] On-chip memory is a sensitive unit within the processor. On-chip memory usually occupies a large amount of area in the entire processor and is vulnerable to high-energy particles, cosmic rays, and other factors. Especially as the feature size of integrated circuits shrinks sharply, decreasing power supply voltage, increasing operating frequency, decreasing node capacitance and rapidly increasing chip transistor capacity make memory cells more and more sensitive to the working environment. Therefore, in order to improve the reliability of the processor, the on-chip memory needs to be hardened for fault tolerance. Moreover, in m...

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Problems solved by technology

In this way, the core algorithm instruction needs to have multiple control fields, and the instruction encoding field is longer; while the general instruction function is simple, the encoding field is shorter

This further increases the vulnerability of digital signal processor instructions, because once an error occurs in the field for distinguishing long and short instructions, the digital signal processor will not be able to distinguish and access subsequent instructions according to the correct width, resulting in abnormal program execution

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