Methods and apparatus for a configurable high-side nmos gate control with improved gate to source voltage regulation

A gate voltage, voltage technology used in the field of configurable n-channel MOSFET gate driver control

Active Publication Date: 2018-04-17
TEXAS INSTR INC
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  • Summary
  • Abstract
  • Description
  • Claims
  • Application Information

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Problems solved by technology

oscillator is coupled to generate the clock signal

Method used

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  • Methods and apparatus for a configurable high-side nmos gate control with improved gate to source voltage regulation
  • Methods and apparatus for a configurable high-side nmos gate control with improved gate to source voltage regulation
  • Methods and apparatus for a configurable high-side nmos gate control with improved gate to source voltage regulation

Examples

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Embodiment Construction

[0011] Corresponding numerals and symbols in the different figures generally refer to corresponding parts unless otherwise indicated. The drawings are not necessarily drawn to scale.

[0012] The term "coupled" may encompass established connections with intermediate elements, and there may be additional elements and various connections between any elements being "coupled".

[0013] To ensure that sufficient voltage with sufficient current drive is always available for an NFET configured as a high-side driver, the gate driver circuit can use a charge pump to provide the necessary gate-to-source voltage (V GS ). Depending on NFET characteristics, additional circuitry may be required to limit V GS To prevent overvoltage damage to the gate structure. V GS A value in the range of 2V to 10V is suitable, depending on the NFET vendor and application. When the high-side driver circuit is active and delivering power to the load, the V GS Maintaining the NFET just in the "on" regio...

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Abstract

In described examples, a transistor (320) has: a source and a drain coupled between a supply voltage and an output terminal; and a gate terminal. A charge pump (314) has: an output node (VGATE) coupled to the gate terminal; and a clock input. An oscillator (310) is coupled to generate a clock signal. A clock enable circuit (312) is coupled to: receive the clock signal; and selectively output the clock signal to the clock input, responsive to an enable signal. A comparator (360) is coupled to output the enable signal in response to a comparison between a reference current and a current througha series resistor (R1). The series resistor (R1) is coupled to the gate terminal.

Description

technical field [0001] The present application relates generally to electronic circuits for controlling gate voltage, and more particularly to configurable n-channel MOSFET gate driver control with improved regulation, accuracy and efficiency. Background technique [0002] N-channel enhancement mode metal oxide semiconductor field effect transistors (n-channel MOSFETs) are widely used in load switching applications due to their low on-resistance and compact size. When an n-channel MOSFET (NFET) is placed between the voltage supply terminal and the load, it is called a "high-side" driver. In this configuration, the source voltage of the NFET depends on the load resistance and load current. In order to turn on an NFET, the gate voltage of the NFET must have a sufficiently high voltage such that the voltage from the gate to the source (Vgs) is greater than the threshold voltage (Vt) of the NFET. Contents of the invention [0003] In the depicted example, the transistor has:...

Claims

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Application Information

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IPC IPC(8): G05F1/575
CPCH02M1/08H03K17/0822H03K3/02337
Inventor E·O·伯吉R·K·森J·路比
Owner TEXAS INSTR INC
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