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Manufacturing method of complementary CMOS tube

A manufacturing method and technology for transistors, applied in semiconductor/solid-state device manufacturing, nanotechnology for materials and surface science, electrical components, etc., and can solve problems such as inability to effectively control short-channel effects

Active Publication Date: 2018-04-27
ZING SEMICON CORP
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  • Summary
  • Abstract
  • Description
  • Claims
  • Application Information

AI Technical Summary

Problems solved by technology

For planar HEMTs, there are still short channel effects that cannot be effectively controlled

Method used

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  • Manufacturing method of complementary CMOS tube
  • Manufacturing method of complementary CMOS tube
  • Manufacturing method of complementary CMOS tube

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Embodiment Construction

[0098] The manufacturing method of the complementary CMOS transistor proposed by the present invention will be further described in detail below with reference to the accompanying drawings and specific embodiments. Advantages and features of the present invention will be apparent from the following description and claims. It should be noted that all the drawings are in a very simplified form and use imprecise scales, and are only used to facilitate and clearly assist the purpose of illustrating the embodiments of the present invention.

[0099] This embodiment provides a method for manufacturing a complementary CMOS transistor, the method for manufacturing a complementary CMOS transistor includes: providing a first germanium nanowire A and a second germanium nanowire B on the same semiconductor substrate, so that the An N-type InGaAs quantum well transistor is formed around the first germanium nanowire A and a P-type germanium junctionless transistor is formed around the secon...

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Abstract

The invention provides a manufacturing method of a complementary CMOS tube. The manufacturing method of the complementary CMOS tube comprises the following steps: providing a first germanium nanowireand a second germanium nanowire positioned on the same semiconductor substrate so that an N-type indium-gallium-arsenic quantum well transistor is formed around the first germanium nanowire and a P-type germanium junction-free transistor is formed around the second germanium nanowire. The complementary CMOS tube manufactured by the method can be used for gate control preferably and is applicable for low power consumption logic application, so that the static electric field is obviously improved, and the complementary CMOS tube has preferable control capacity for short channels.

Description

technical field [0001] The invention relates to the technical field of semiconductors, in particular to a manufacturing method of a complementary CMOS transistor. Background technique [0002] It is hoped that by adopting an ultra-thin body (UTB) such as a quantum well structure, the more serious short-channel effect caused by the MOS transistor continuing to be scaled down to a smaller size is avoided. The basic structure of a high electron mobility transistor (HEMT) consists of a modulation-doped heterojunction and its source-drain structure. The two-dimensional electron gas (2-DEG) existing in the modulated doped heterojunction has a very high mobility due to being unaffected by the scattering of ionized impurity ions. HEMT is a planar voltage-controlled device. The gate voltage Vg can control the depth of the heterojunction potential well, thereby controlling the surface density of 2-DEG in the potential well, and then controlling the working current of the device. [...

Claims

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Application Information

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Patent Type & Authority Applications(China)
IPC IPC(8): H01L21/8238B82Y30/00
CPCB82Y30/00H01L21/823807
Inventor 肖德元
Owner ZING SEMICON CORP