DSP processor data memory active fault tolerance method and device

Abstract

The invention provides a DSP data memory active fault-tolerant method and device. The device is arranged between a DSP core assembly line and an intra-core data memory and is used for active fault-tolerant refreshing of the data memory. The device comprises a LOAD instruction code used for loading the data memory, a STORE instruction code for writing the data memory, a queue access module, an RSECinstruction decoding module, the data memory, a data error correction and detection, a universal register file, a correctable error state register, a circulating Record queue, a data memory writing operation module and an interrupt processing module used for hardware interrupt. The frequency performance of a DSP is basically not influenced through proper assembly line partitioning. According to the method and device, the fault-tolerant processing strategy and time of hardware can be flexibly controlled, the requirement for system reliability is met at a relatively low cost, and the executionefficiency of the DSP under an error abnormal condition is ensured.

Description

technical field [0001] The invention belongs to the technical field of microelectronics and relates to a highly reliable and high-performance processor fault-tolerant structure, in particular to a DSP processor data memory active fault-tolerant method and device. Background technique [0002] Memory is the most sensitive part of a modern processor. Especially with the continuous improvement of the semiconductor manufacturing process, the feature size of the integrated circuit is shrinking sharply. On the one hand, the ever-decreasing power supply voltage, ever-increasing operating frequency, ever-decreasing node capacitance, and rapidly increasing chip transistor capacity in nano-integrated circuits make memory cells more and more sensitive to the working environment. When the memory circuit is impacted by high-energy particles, power supply noise, electromagnetic influence or cosmic rays, the content stored in the memory unit of the chip will be destroyed transiently or pe...

AI Technical Summary

Problems solved by technology

Simply flushing the pipeline will "waste" instructions already in the pipeline

[0005] Most DSP processors have only one level memory structure, such as "MSC8102Technical Data" released by Freescale in 2005, "TriMedia TM-1300" released by Philips in 2000, "TMS320C6000 CPU and Instruction Set Reference" released by Texas Instruments in 2000 Guide”, which does not update and write back the data memory in time, which will lead to the cumulative effect of memory errors

If in order to avoid error events, disable the on-chip first-level storage and fetch data from the external memory, although the correct data can be obtained, it will cause a large memory access delay, which is not conducive to the performance of the DSP processor.

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