A Method for Improving Wafer Jitter in Tunneling Oxide Growth Process

A tunneling oxide layer and process technology, which is applied in the manufacture of electrical components, circuits, semiconductors/solid-state devices, etc., can solve wafer deformation, affect product silicon chip edge coverage yield, and wafer deformation ISSG process is difficult to solve, etc. problem, to achieve the effect of improving the yield rate

Active Publication Date: 2021-04-06
WUHAN XINXIN SEMICON MFG CO LTD
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  • Application Information

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Problems solved by technology

At present, in the industry, the in-situ steam generation (ISSG, in-situ steam generation) annealing process is usually used to make the tunneling oxide layer. The wafer deformation problem has always been a difficult problem in the ISSG process, which determines whether the subsequent process The ability to proceed smoothly also affects the overlay and yield of the edge of the product silicon wafer
The conversion of gas in the process will cause changes in air pressure, such as Figure 1-5 As shown, the high-speed rotating wafer (wafer) shakes, which in turn causes the wafer to deform at high temperature

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  • A Method for Improving Wafer Jitter in Tunneling Oxide Growth Process
  • A Method for Improving Wafer Jitter in Tunneling Oxide Growth Process
  • A Method for Improving Wafer Jitter in Tunneling Oxide Growth Process

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Embodiment Construction

[0034] The invention provides a method for improving wafer shaking in the growth process of the tunnel oxide layer.

[0035] In the following, the present invention will be described in detail and specifically through specific examples, so as to better understand the present invention, but the following examples do not limit the scope of the present invention.

[0036] Such as Figure 8 As shown, a method for improving wafer jitter in the tunnel oxide growth process of the present invention comprises the following steps:

[0037] S1 performing a tunneling oxide layer growth process on a semiconductor substrate;

[0038] S2 performing an annealing process on the semiconductor substrate that has undergone the tunneling oxide layer growth process in step S1: heating the reaction chamber, and simultaneously feeding hydrogen and oxygen to keep the pressure in the reaction chamber constant;

[0039] S3 annealing reaction for a certain period of time;

[0040] S4 stops heating the...

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Abstract

The invention discloses a method for improving wafer shaking in a tunneling oxide layer growth process, which comprises the following steps: firstly performing a tunneling oxide layer growth process on a semiconductor substrate; and then performing the tunneling oxide layer growth process on all The annealing process of the above-mentioned semiconductor substrate: heating the reaction chamber, feeding hydrogen and oxygen at the same time, so that the air pressure in the reaction chamber remains constant; annealing reaction for a certain period of time; stopping heating the reaction chamber to reduce the temperature in the reaction chamber ; Turn off the hydrogen, reduce the amount of oxygen ventilation, and feed nitrogen at the same time, so that the pressure in the reaction chamber remains constant; after cooling down, the annealing process is completed. The present invention improves the ISSG annealing process. Through the technical analysis and understanding of the wafer deformation, after finding the cause of the defect, the process flow and parameters are changed to solve the problem of silicon wafer shaking during the high-temperature process. After using this method , The yield rate of silicon wafers can be increased by more than 5%.

Description

technical field [0001] The invention relates to a semiconductor process, in particular to a method for improving wafer shaking in a tunnel oxide layer growth process. Background technique [0002] For floating gate (floating gate) products, tunnel oxide (TUNNEL OX, tunnel oxide) is a crucial core process in the entire process, and the temperature uniformity during the growth of tunnel oxide (TUNNEL OX) is the key Index, which determines the quality of the edge growth coverage (overlay) in the subsequent lithography (Litho) process, and also affects the defects and product yield at the edge of the product silicon wafer. At present, in the industry, the tunnel oxide layer is usually made using In-situ steam generation (ISSG, in-situ steam generation) annealing process, the wafer deformation problem has always been a difficult problem in the ISSG process. It determines whether the subsequent process can go smoothly, and also affects the edge of the product silicon wafer. Cover...

Claims

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Application Information

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Patent Type & Authority Patents(China)
IPC IPC(8): H01L21/67
CPCH01L21/67248
Inventor 马鸣明张伟光
Owner WUHAN XINXIN SEMICON MFG CO LTD
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