Semiconductor structures and methods of forming them

Abstract

The invention provides a semiconductor structure and a forming method thereof. The forming method comprises the steps of: providing a substrate, wherein the substrate comprises isolation regions and device regions, the isolation regions are in contact with the device regions, and fin portions are arranged on the substrate in the device regions; forming initial isolation structures on the substrate; performing primary etching on the initial isolation structures in the isolation regions so that the surfaces of the initial isolation structures in the isolation regions are lower than the surfacesof the initial isolation structures in the device regions, and forming an isolation groove and an isolation layer positioned at the bottom part of the isolation groove in each initial isolation structure in the isolation regions; forming a protection layer in each isolation groove; and performing secondary etching on the initial isolation structures in the isolation regions after the protection layers are formed, wherein an etching rate of the protection layers is less than an etching rate of the initial isolation structures. By etching the isolation structures in the isolation regions, the height of the initial isolation structures in the isolation regions can be reduced, so that the side walls of the isolation layers are not prone to expose by the secondary etching, further the loss of the isolation layers in the isolation regions caused by the secondary etching can be reduced.

Description

technical field [0001] The invention relates to the technical field of semiconductor manufacturing, in particular to a semiconductor structure and a forming method thereof. Background technique [0002] As the integration level of semiconductor devices increases, the critical dimensions of transistors continue to shrink. However, as the size of the transistor decreases sharply, the thickness of the gate dielectric layer and the operating voltage cannot be changed accordingly, which makes it more difficult to suppress the short channel effect and increases the channel leakage current of the transistor. [0003] The gate of the Fin Field-Effect Transistor (FinFET) has a forked 3D structure similar to a fish fin. The channel of the FinFET protrudes from the surface of the substrate to form a fin, and the gate covers the top surface and sidewall of the fin, so that the inversion layer is formed on each side of the channel, and the connection of the circuit can be controlled on ...

AI Technical Summary

Problems solved by technology

[0005] However, the performance of the semiconductor structure formed by the existing method for forming the semiconductor structure is poor

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