Synchronous serial bus receiving end anti-interference design method
A technology of synchronous serial port and design method, applied in instruments, electrical digital data processing and other directions, can solve the problems of small number of ground wires, distortion of the transmission signal edge, inability to meet impedance matching, etc., to improve accuracy, reliability, resistance to Strong pulse interference ability and the effect of filtering out occasional burrs
Active Publication Date: 2018-06-08
XIAN INSTITUE OF SPACE RADIO TECH
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Problems solved by technology
However, in some specific applications, such as satellite payload cabins that have strict requirements on space layout and wiring, due to the limitations of the physical location of multiple receivers / transmitters and the requirements of bus harnesses, traditional chain topology cannot be used structure, the length of each branch line on the bus cannot meet the requirements of impedance matching, and the number of ground wires is small, resulting in distortion of the transmission signal edge on the bus, and glitch interference may be superimposed on the transmission signal
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[0046] The core of the present invention is to adopt a unified clock to carry out time-division sampling and three-mode consistency judgment method and strategy in the FPGA chip to receive the RS422 / RS485 standard synchronous serial port signal under the control of the internal enable signal, and the detailed steps are as follows:
[0047] Step 1: Use a typical RS422 / RS485 standard interface chip to convert the synchronous serial bus signal into an LVTTL signal level and input it into the FPGA chip, record the main frequency of the FPGA signal input as f clk , the synchronous serial port signals received from the RS422 / RS485 bus and converted by the interface chip are:
[0048] rs_clk (synchronous clock signal), rs_en (synchronous enable signal), rs_data (synchronous data signal);
[0049] Step 2: For f clk The signal is frequency-divided to generate a width of f clk Clock width, frequency at least 100 times synchronous serial bus synchronous clock frequency, maximum f clk ...
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The invention discloses a synchronous serial bus receiving end anti-interference design method. On the condition that a bus topology structure is not normalized and a synchronous serial bus clock is low in speed, a standard hardware receiving circuit is unchanged, enabling control, a unified clock, time sampling and three-modular judgment are adopted to process a synchronous serial bus signal in an FPGA chip, and the correctness and reliability of signal receiving are improved; a peripheral RS422 / RS485 standard synchronous serial bus topology structure is loose in constraint, and the length of each branch on the bus is not strictly limited. The pulse anti-interference capability is high, and accidental burrs on the bus can be filtered out.
Description
technical field [0001] The invention relates to an anti-interference design method for a synchronous serial bus receiving end, belonging to the technical field of bus receiving and processing. Background technique [0002] The RS422 / 485 standard is a digital communication electrical standard introduced by the Electronics Industries Association (EIA) in the late 1970s. This standard uses a balanced drive differential receiving circuit, which has many advantages such as strong anti-common-mode interference ability, strong driving ability, long transmission distance, support for bus transmission, and good signal tolerance. It is currently widely used in various industrial control data communication occasions. [0003] At present, there are several methods to solve the problem of monotonic flipping of transmission signal edges on the RS422 / RS485 interface bus and the problem of occasional glitch interference: [0004] ①In the receiving / transmitting end of the RS422 / RS485 standa...
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IPC IPC(8): G06F13/42
CPCG06F13/4291
Inventor 邢炜张攀刘洋王延光李阳王登峰
Owner XIAN INSTITUE OF SPACE RADIO TECH