Parallel port synchronizing method, circuit and chip for transmitting end in multi-channel high-speed serial bus

Abstract

The invention relates to a parallel port synchronizing method, circuit and chip for a transmitting end in a multi-channel high-speed serial bus. In the prior art, a cache is generally used to implement parallel port synchronization. However, the cache often occupies much chip area so that the cost is increased. In the parallel port synchronizing method, circuit and chip, only a plurality of logical gates are used by the circuit / chip; in cooperation with automatic phase position detection, a parallel clock phase position is dynamically adjusted in an actual working process, thereby implementingthe port synchronization. By adopting the method, the circuit and the chip provided by the invention, problems of the parallel port synchronization and clock domain crossing are solved simultaneously, the use of the cache is prevented, and the resource overhead and the link delay are reduced; and a phase position relationship between clocks is adjusted automatically in the actual working process,so a system is guaranteed not to be influenced by a voltage, a temperature and a process deviation.

Description

technical field [0001] The invention belongs to the field of integrated circuit design, and in particular relates to the design of a physical layer in a high-speed serial bus, especially a method, a circuit and a chip for synchronizing a parallel data port of a sending end in the physical layer. Background technique [0002] In the field of communication, serial communication refers to a communication method in which only one bit of data is sent at a time when sending data. Now, more and more parallel bus structures are replaced by serial buses, such as PCIe, SATA and USB, etc. The serial bus usually uses SerDes as the physical layer basis, and the communication medium is usually the traces on the printed circuit board, the backplane or the cable. The communication adopts point-to-point topology, differential routing, and there is no problem of clock skew. At the same time, the clock signal does not need to be sent simultaneously with the data, and the receiving end will e...

AI Technical Summary

Problems solved by technology

By adopting the method, circuit and chip of the present invention, the problems of parallel port synchronization and clock domain crossing are solved at the same time, the use of buffers is avoided, resource overhead and link delay are reduced, and the clock interval is automatically adjusted in the actual working process. The phase relationship ensures that the system is not affected by voltage, temperature and process deviation

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