Lightweight hashed password digest generation method

A lightweight, hash technology, applied in the field of lightweight hash password digest generation, which can solve problems such as increasing running time and power consumption, and conforming to algorithm parameters.

Inactive Publication Date: 2018-08-24
INST OF SOFTWARE - CHINESE ACAD OF SCI
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  • Description
  • Claims
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Problems solved by technology

[0005] However, for a specific application environment such as a low-power secure embedded processor chip, the instruction data processed by it has a fixed format, the data length is 64 bits or its multiple, and the summary length does not need to be too long, so the above-mentioned general l

Method used

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  • Lightweight hashed password digest generation method
  • Lightweight hashed password digest generation method
  • Lightweight hashed password digest generation method

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Embodiment Construction

[0051] The present invention will be described in detail below through specific implementation examples.

[0052] The processing method of this implementation example is as follows:

[0053] Step 1: Divide the input message M into 64-bit message blocks m 0 ,m 1 ,...,m i . Set the initial state S 0 A 96-bit string of all zeros.

[0054] Step 2: Block the message m j XOR to S j On the high-order 64 bits, the state after XOR is used as the input S of the internal permutation IP j ', where 0≤j≤i.

[0055] Step 3: Enter 96 bits into state S j 'Equally divided into two parts, which are respectively recorded as the left half branch L and the right half branch R, wherein both L and R are 48-bit strings.

[0056] Step 4: Combine the upper 16 bits of the left half branch L with the round constant C r (1≤r≤18) XOR, the output after XOR is used as the input of position replacement P.

[0057] Step 5: Divide the 48-bit input of position replacement P into 12 groups according to...

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Abstract

The invention discloses a lightweight hashed password digest generation method. The method comprises the following steps: 1) dividing an input message M into a plurality of 64-bit message blocks, setting a 96-bit state parameter S<j> and initializing the 96-bit state parameter S<j> into an all-zero 96-bit string; 2) sequentially processing the message blocks, transforming the message blocks m<j> onto a high-bit 64 bit of the S<j> in an XOR manner, and taking the S<j> being subjected to the XOR processing as the input of internal replacement IP, wherein j is more than or equal to 0 and less than or equal to i, the internal replacement IP adopts a 18-wheel Feistel structure, and the output of the internal replacement IP is updated S<j>; and 3) taking a high 16 bit of a state S<j> obtained after processing of the last m as the digest of the message M. The method is implemented in one clock cycle, and the operation efficiency of an embedded processor chip is increased.

Description

technical field [0001] The invention proposes a light-weight hash cipher digest generation method suitable for low-power consumption safety embedded processor chips, which belongs to the technical field of communication. Background technique [0002] Since the advent of the microprocessor, the embedded system has developed rapidly and has been widely used in various fields of our life, such as: industrial control, smart card, automobile industry and so on. The embedded processor is the core part of the embedded system, which is directly related to the performance and safety of the entire embedded system. Embedded processors are a kind of resource-constrained devices, which have common characteristics, that is, very limited computing power and storage space, and strict requirements on cost and power consumption control. These new computing and application environments also put forward new requirements for security: because there is no need to deal with highly capable attacke...

Claims

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Application Information

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IPC IPC(8): H04L9/06G06F21/64G06F21/10
CPCG06F21/10G06F21/64H04L9/0618H04L9/0643
Inventor 吴文玲张蕾郑雅菲
Owner INST OF SOFTWARE - CHINESE ACAD OF SCI
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