A framework and method for performance optimization of grid applications on many-core architecture

Abstract

The present invention provides a framework for performance optimization of grid application programs on many-core architectures, including an application field description layer, a programming model layer, a hardware architecture layer, and a converter; (1) the user uses the application field of the application field description layer Describe, in the case of only considering the domain programming, write the program to solve the domain problem; (2) The converter converts the user program into the code of the programming model layer based on the programming environment combination; (3) the programming model layer The code is compiled with the compiler of the corresponding programming environment, and linked with the corresponding dynamic library, and finally generates the code that can run at the hardware architecture layer; (4) through the mapping relationship between the performance model and the efficiency model, the converted programming The program at the model layer is manually optimized and adjusted, or even automatically iteratively optimized and adjusted through the converter.

Description

technical field [0001] The present invention relates to the field of computer technology, more specifically, to a performance optimization framework and method for a grid application program on a many-core architecture. Background technique [0002] Mesh-based large-scale numerical simulation calculations are playing an increasingly important role in the development of modern science, such as the aerodynamic research of aerospace vehicles, and the cavitation research of ship propellers. In this kind of calculation, the shape of the solution is complex, the required solution accuracy is high, and the size of the grid can reach hundreds of millions or even tens of billions, which leads to the need for extremely strong computing power in this application field. Now the increasingly mature many-core architecture is a typical large-scale parallel computing unit. To make good use of its parallel computing capabilities, performance-optimized application programming for this archit...

AI Technical Summary

Problems solved by technology

When it runs on a many-core architecture with a vectorized processing unit width of 256bit, the program can make full use of the vectorized unit, but when it runs on a many-core architecture with a vectorized processing unit width of 512bit , it does not make full use of its vectorization unit, so that the efficiency improvement is not optimal

[0007] Second, they lack overall consideration of performance optimization and lack of modeling guidance

In terms of many-core architecture, there is no efficiency model describing its system parameters.

This makes it difficult for them to further optimize the converted program for the hardware architecture efficiently.

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