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Hardware Trojan horse detection method and a device of a key node based on power consumption average analysis

A hardware Trojan detection and key node technology, applied in the direction of platform integrity maintenance, etc., can solve the problems of high engineering cost, low detection accuracy, and narrow application range, and achieve low engineering cost, high detection accuracy, and wide application range. Effect

Inactive Publication Date: 2018-12-14
PHYTIUM TECH CO LTD
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  • Claims
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Problems solved by technology

[0004] The technical problem to be solved by the present invention: Aiming at the problems of high engineering cost, narrow application range, and low detection accuracy in the prior art, a method and device for detecting hardware Trojan horses of key nodes based on power consumption average analysis are provided. The present invention has engineering cost Advantages of low cost, wide application range and high detection accuracy

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  • Hardware Trojan horse detection method and a device of a key node based on power consumption average analysis
  • Hardware Trojan horse detection method and a device of a key node based on power consumption average analysis
  • Hardware Trojan horse detection method and a device of a key node based on power consumption average analysis

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Embodiment 1

[0029] In the following, the AES (Advanced Encryption Standard) encryption chip will be used as an example to further describe in detail the method and device for detecting hardware Trojan horses at key nodes based on average power consumption analysis of the present invention.

[0030] Such as figure 1 As shown, the implementation steps of the key node hardware Trojan horse detection method based on power consumption average analysis in this embodiment include:

[0031] 1) For the chip to be tested, select a pure reference chip ("pure" chip) that is confirmed to be free of hardware Trojans;

[0032] 2) Key nodes selected for the chip to be tested;

[0033] 3) Apply incentives to the pure reference chip and sample the power consumption data of the pure reference chip to obtain the power consumption data K of the corresponding key node when the logic value jumps 1 , The power consumption data K when the logic value does not jump 2 , the power consumption data K 1 , power co...

Embodiment 2

[0059] This embodiment is basically the same as Embodiment 1, and the main difference is: this embodiment performs batch detection for batches of chips to be tested. In order to simulate other batches of 9 chips to be tested, the AES encryption chip is introduced into the process deviation using the Monte Carlo random method, and the 9 chips to be tested from other batches are simulated. Such as image 3 As shown, the s-box module in the AES encryption circuit of the specific implementation step 2) selects the highest bit (out[7]) of one of the 8-bit output ports as a key node, and the remaining 7 bits (out[6:0]) as a reference node. Utilize the Virtuoso tool to attach a hardware Trojan horse (1 inverter) to the key node of the encrypted circuit layout.

[0060] Such as Figure 4 As shown, when obtaining the power consumption data K in this embodiment: use the Caliber tool to perform capacitance (C) and resistance (R) parasitic parameter extraction (RC extraction) on the "p...

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Abstract

The invention discloses a hardware Trojan horse detection method and a device of a key node based on power consumption average analysis. The detection method of the invention comprises the steps of: selecting and confirming the pure reference chip without hardware Trojan horse according to the chip to be tested; for the key nodes selected by the chip to be tested according to the pure reference chip, obtaining the the power consumption data K1 during logic value transition and the power dissipation data K2 when the logic value does not jump of the corresponding key nodes, taking the mean difference of the power consumption data K1 and the power consumption data K2 to obtain a reference power consumption data K, obtaining the power consumption data P1 of the key node of the chip to be tested when the logic value transitions and the power consumption data P2 when the logic value does not jump, taking the mean difference of the power consumption data P1 and the power consumption data P2 to obtain the measured power consumption data P, obtaining the difference of the measured power consumption data P and the reference power consumption data K, and if the power consumption spike occursin the difference, determining that the hardware Trojan horse exists in the chip to be tested. The invention has the advantages of low engineering cost, wide application range and high detection accuracy.

Description

technical field [0001] The invention relates to the field of chip security detection, in particular to a method and device for detecting a key node hardware Trojan horse based on power consumption average value analysis. Background technique [0002] With the rapid increase in the application of chips in the information industry, its security has become the lifeblood of the survival and development of many industries. Today's chip design and manufacturing process has been divided into multiple stages. Chip front-end logical design, back-end physical design, packaging and testing may be completed by different companies or units, and malicious tampering of hardware circuits may occur in every step of the chip supply chain. This kind of malicious tampering (also known as hardware Trojan horse) can leak secret information or cause circuit dysfunction or even self-destruction through the hidden channel inside the chip. Today, chips have become the backbone of digital globalizat...

Claims

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Application Information

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Patent Type & Authority Applications(China)
IPC IPC(8): G06F21/56
CPCG06F21/56
Inventor 李水晶涛高军赵天磊薛洪波孙龙鹏
Owner PHYTIUM TECH CO LTD
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