A high speed memory chip having multiple independent access channels

Abstract

The invention relates to the field of computer system structure and integrated circuit design, and a high-speed memory chip having a plurality of independent access channels is disclosed, including anon-chip memory and several high-speed serial access channels. A network-on-chip interconnect module is also included. The on-chip memory includes a plurality of memory sub-blocks accessible in parallel, and the memory sub-blocks and the high speed serial access channels are interconnected by the on-chip interconnect network module, and the on-chip interconnect network module being implemented ina single bus, a multi-bus, a ring network, a two-dimensional mesh, or a crossbar switch. The invention has a high-speed memory chip with a plurality of independent access channels, has good bandwidthexpansibility, realizes the shared parallel access of a plurality of main control chips to the memory chip and the data sharing and exchange among the plurality of main control chips, integrates storage and processing, and reduces the total storage cost of the system and the design and manufacture cost of the memory chip.

Description

technical field [0001] The invention relates to the field of computer system structure and integrated circuit design, in particular to a high-speed memory chip with multiple independent access channels. Background technique [0002] In a computer system, the storage subsystem plays a very important role and plays a very important role in the overall performance of the system, especially for those memory-intensive algorithms, the memory access bandwidth and delay are the key factors that determine the performance of the algorithm. Judging from the status quo of technological development, the improvement of storage performance lags far behind the improvement of computing performance. [0003] The industry develops new storage technologies from a variety of different technical approaches, such as DDR4 / DDR5, GDDR5, HMC (Hybrid Memory Cube), HBM (High Bandwidth Memory), etc. Although various new storage technologies can improve memory access bandwidth higher and higher, there ar...

AI Technical Summary

Problems solved by technology

First, the bandwidth improvement of these storage technologies is limited. They use a multi-bit parallel interface bus. The main way to further increase the bandwidth is to use a wider interface bus or increase the interface rate, but the multi-bit parallel bonded transmission requires signal integrity. It is becoming more and more difficult to implement higher, wider and higher-speed interfaces

Second, the implementation cost of new storage technology is relatively high. For example, the engineering cost of advanced HBM technology is as high as tens of millions of dollars.

The third is that the above-mentioned new storage technologies do not have a sharing mode, or the sharing granularity is very low. For example, DDR4 / DDR5, GDDR5, and HBM storage media can only be accessed by the main control chip directly connected to them, and cannot realize multiple storage. Direct shared access of multiple main control chips; although HMC can support the connection of multiple main control chips, it does not support the shared use of more than four main control chips

In addition, limited by the production capacity of storage suppliers, storage is in an unbalanced state of supply and demand, which pushes up the selling price of storage, making the cost of storage in the system more and more high, and the cost of the above-mentioned new types of storage is even higher. It also severely restricts the large-scale application of new storage technologies and memory chip products.

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